Vybrid M4 core Cache Mapping

[stefansinger]

Hi all, we are trying to understand, how cache mapping for the Cortex M4 core works on Vybrid. I am somewhat new to Vybrid, so the question might be simple (my personal background is mainly Power Architecture). Chapter 29 of the Vybrid RM describes the Local Memory Controller and describes static "views" of the memory, whether a certain region is non-cachable, write through, ... I can not find any setting to mark e.g. the GFX RAM non cachable. I also tried to compare the description to the Kinetis RM and there is an additional register "Cache regions mode register (LMEM_PSCRMR)", which allows to map those sections, but that register seems to be missing on Vybrid ? I have heard some comments, that the M4 core on Vybrid has an MPU and the one on Kinetis has not, so that function might be in the MPU now ? According the ARMs Cortex M documentation there should be the MPU_RASR.ATTRS fields in the MPU to define those attributes. Are those implemented on Vybrid and is there an example, how to configure this ?

Thanks in advance

Stefan

[jiri-b36968]

Hi Stefan,

unfortunately individual setting on regions for CM4 core is not possible. You can separately enable or disable code and data cache. You can also force cachable regions to write-through. Instead of MPU there are CSU (Central Security Unit) and AHB-TZASC (AHB-TrustZone Address Space Controller) modules. Described in Vybrid Security Reference Manual.

/Jiri

[zeeshanaslam]

Hi Jiri,

Please tell me if I got it right.

There is no MPU implemented on Vybrid, instead there is CSU and AHB-TZASC to implement corresponding memory access features as MPU. So, is there any way supported to configure cacheable attributes (write-back, write-through, no-cache) of different memory regions for CM4, different from caches mode at reset. I mean through CSU and AHB-TZASC, in a similar way as we do it with MPU. Or simply, there is no way supported?

You response will be highly appreciated!

Best regards,

Zeeshan Aslam

[jiri-b36968]

Hi Aslam,

yer, that is right, no "MPU" but CSU and AHB-TZASC.

Regarding cache on CM4 core. It is controller by Local memory controller. You can use predefined setting of regions (see RM Table 29-1. Address Space Decode). Or you can disable cache so all region are non cached. Or you can force all cacheable regions to write-through (LMEM_PCCCR PCCR2).

/Jiri

[stefansinger]

Hi Jiri,

if I look with a debugger into the memory region, which is documented for Kinetis as LMEM_PSCRMR. Are you sure, that in fact it does not provide the same feature as on Kinetis ? The problem however is now, that the region description for that register is of course totally missing in the Vybrid RM.

Stefan

[jiri-b36968 · Accepted solution]

Hi Stefan,

it was designer's reply couple of months ago and as you say - registers are not in RM.

/Jiri