Vybrid Bare-Metal MMU (Direct Mapping)

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Vybrid Bare-Metal MMU (Direct Mapping)

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ChrisNielsen
Contributor III

I have created what I thought was a direct mapping of all items in the Vybrid memory map (virtual address = physical address) [LOTS of typing!].  I am running in bare-metal mode, no Linux.  I have no interest in the MMU and would have preferred to ignore it and keep it disabled; however, loading and enabling the MMU is required to be able to use L2 cache...so in I went, and it works, and runs much faster.

 

The translation works fine for sysRAM0, sysRAM1, and GPIOs.  I recently added a few UART register writes and it hangs my system.  I disabled the MMU translation and it works fine, so I'm assuming that the UART register access is causing an MMU violation (unrecognized address).

 

I've stared at it quite a bit and triple checked it and I can't find the bug.  Attached is the code.

 

I suppose I could define an extremely simple L1 that just maps a single block, the entire chip's address space, but I really would like to maintain the trapping of execution of invalid addresses as opposed to debugging random behavior related to hitting undefined addresses.

 

Is anyone else running in bare metal mode?

 

Thanks for any help, Chris

Original Attachment has been moved to: MMU_init_code_fragment.c.zip

Original Attachment has been moved to: ttbl.h.zip

Original Attachment has been moved to: ttbl-Vybrid.c.zip

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ChrisNielsen
Contributor III

I got it working.  I used the poor protection method and just defined 1MB umbrella sections at the L1 table level (no L2 tables) to cover the two peripheral areas (IPS0, IPS1) and the extra on-board RAM (sysRAM0, sysRAM1).  I also made a proper init package with error checking on the CP15 calls.  Maybe this code can help one other intrepid bare-metal soul...Enjoy, Chris

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ChrisNielsen
Contributor III

I got it working.  I used the poor protection method and just defined 1MB umbrella sections at the L1 table level (no L2 tables) to cover the two peripheral areas (IPS0, IPS1) and the extra on-board RAM (sysRAM0, sysRAM1).  I also made a proper init package with error checking on the CP15 calls.  Maybe this code can help one other intrepid bare-metal soul...Enjoy, Chris

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paulholmquist
Contributor I

Chris, you posted a link to this as a possible solution to my post for help on enabling-cache (speed up GPIO) which is what I eventually need to do...(may need to replace MQX with different kernel).  Thanks very much for the help.

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ChrisNielsen
Contributor III

Regarding:

Where do I get a copy of the "armv7a_cp15_drv.h" include file?  The code above also references "functions.h" but doesn't look like I'll need that.

Unfortunately those are IAR copyrighted files (you need armv7a_cp15_drv.h/c).  I'm sorry.  I forgot about those.  Maybe we'll get lucky and Freescale has a relationship with IAR that allows sharing of common example files, such as these.

Freescale, can these files be shared?

Chris

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