I would like to profile the A5 core of my Vybrid VF6xx by periodically sampling the program counter (PC).
I see from the "ARMv7-M architecture reference manual" and the "Vybrid reference manual (section 20.9)" that the M4 core provides a Data Watchpoint and Trace (DWT) unit that can be configured to sample the PC at regular intervals. The sampled PC can then be streamed to the SWO interface which I can read with my debugger. This is exactly what I would like to do with the A5 core, instead of the M4.
Is there any way to achieve the same result (stream of PC information to SWO) with the A5 core? As far as I understand the A5 does provide a program counter sampling register (DBGPCSR), but lacks of a mechanism to stream it. Am I wrong?
Best regards
Kean Mariotti
