HI,
Trying to force a reset using the SRC Control Register, setting the SW_RST bit, doesn't seem to be successful, the micro doesn't restart and requires a power cycle. We have the M4 as the primary core and A5 as secondary.
Is there anything we are not doing - e.g. putting the micro in a particular state before setting the SW_RST bit?
Solved! Go to Solution.
Hello Neil,
Can you clarify your system environment please? What OS is running on each core?
Allow us time to review, as I am aware of commits against upstream Linux kernel addressing SW_RST for Vybrid.
Regards,
Timesys Support
Hello Neil,
Can you clarify your system environment please? What OS is running on each core?
Allow us time to review, as I am aware of commits against upstream Linux kernel addressing SW_RST for Vybrid.
Regards,
Timesys Support
Hi, thanks for the responses.
Happy to report it is now working, since we added some new bootloader code - i think the problem wasn't in the reset, it was in our startup code.
Cheers
timesyssupport can you help with this case?