MQX application is not booting from QuadSPI_NAND flash

[abdulnihad]

I have developed an mqx based audio application using vybrid tower system.I am using DS5 for my development. I have flashed hello_world application to QuadSPI serial nand flash using quadspi_load application available in the vybrid sample code. hello_world application is booting from quadSPI when I configured J22 jumper for QuadSPI boot. hello_world application is not using mqx.

Now I want to boot my mqx audio application from QuadSPI serial nand flash. SO I added quadspi_boot.c,quadspi_boot.h and sram_ds5_a5.scf file from

Freescale\Freescale_MQX_4_0\mqx\examples\bootloader_vybrid_qspixip application. builded and created c array file using fromelf --cadcombined <audioApp_a5>.axf --output flash_bin.c

I have flashed flash_bin.c using quadspi_load application available in the vybrid sample code.(modified quadspi_load application to accept my flash_bin.c ).

flashing was success. But audio application is not booting from quadSPI when I configured J22 jumper for QuadSPI boot.

Please help me to fix the booting issue.

size of flash_bin.c is 850 KB

size of flash_bin.o is 164 KB ( after compiling using quadspi_load application available in the vybrid sample code)

I am attaching quasdpi_boot.c,quadspi_boot.h and QuadSPI_XIP.scf ( slightly modified version of sram_ds5_a5.scf) which I used in my audio application for reference.

BR/-

Nihad

Original Attachment has been moved to: QuadSPI_XIP.scf.zip

Original Attachment has been moved to: quadspi_boot.c.zip

Original Attachment has been moved to: quadspi_boot.h.zip

[juangutierrez]

The changes in quadspi.c looks good. Make sure your entry point is at 0x20000800, this seems to be the very beginning of your STARTUP section,

I assume the application works when loading to the IRAM. In that case does the entry point is at the top of the STARTUP section or is something else?

Other thing is that make sure the boot sections are being kept and not removing by the linker. Usually you use some linker flags like --keep=.ivt (or something similar)

Also, can you share the flash_bin.o, I would like to check the 0x400 address offset

[abdulnihad]

Thanks Juan for your prompt reply.

How to check entry point is at the top of the STARTUP section?.

I have set '__boot' as entry point under properties->Arm linker->General->Image Entry point (--entry)

Also added entry point as shown below in quadspi_boot.c

const ivt image_vector_table = {

  IVT_HEADER,                        /* IVT Header */

  (uint32_t)0x20000800,    /* Image  Entry Function */

  IVT_RSVD,                          /* Reserved = 0 */

  (uint32_t)0x20000430,              /* Address where DCD information is stored */

  (uint32_t)0x20000420,        /* Address where BOOT Data Structure is stored */

  (uint32_t)0x20000400,      /* Pointer to IVT Self (absolute address */

  (uint32_t)0x00000000,              /* Address where CSF file is stored */

  IVT_RSVD                            /* Reserved = 0 */

};

I have added below lines in properties->Arm linker->Optimization to keep the boot section

quadspi_boot.o(.conf)

quadspi_boot.o(.ivt)

quadspi_boot.o(.boot_data)

quadspi_boot.o(.dcd)

I am Attaching

1) flash_bin.c created using my mqx audio application.

2) flash_bin.o created using quadspi_load application.

3) Also attaching memory map of mqx audio application

[juangutierrez]

The flash_bin files looks good.

Can you try using the __boot symbol in the ivt (as below)

However I don't see this symbol in the map file. Is this a valid symbol?

const ivt image_vector_table = {

  IVT_HEADER,                        /* IVT Header */

  (uint32_t)__boot,    /* Image  Entry Function */

  IVT_RSVD,                          /* Reserved = 0 */

  (uint32_t)0x20000430,              /* Address where DCD information is stored */

  (uint32_t)0x20000420,        /* Address where BOOT Data Structure is stored */

  (uint32_t)0x20000400,      /* Pointer to IVT Self (absolute address */

  (uint32_t)0x00000000,              /* Address where CSF file is stored */

  IVT_RSVD                            /* Reserved = 0 */

};

[juangutierrez · Accepted solution]

I think I found the problem :smileyhappy:

It seems to have a wrong set of values in the quadspi_conf structure

I compared this values against one image that is working for me and they are different, copying the values from the working binary to the binary you provided (patching the binary) I can see the next logs

......................Starting Application................................

on main_task

IPCFG: Device init failed. Error = 0xA414

IPCFG: Failed to bind IP address. Error = 0x1D03

Created ETH_LISTENER_TASK, taskid:0x10003

cmd -> open

Resetting and Latching tuner configuration

TunerCMDListner_task created, id 0x10005

exiting main_task

Initialising Polled I2C driver.........

Set i2c current baud rate to 100000

Set i2c in master mode

Set i2c target address to 0x61

I2C_STATE_READY

tuner opened

cmd -> init

InitTunerI2S error: Unable to open audio device.

Initialising Radio....

RadioInit: Chip Version = cb

rds_task created, id 0x10002

Could not create Tuner_task

init tuner err=-1

cmd -> on

Resetting and Latching tuner configuration

tuner on

This is the configuration that works for me

const SFLASH_CONFIGURATION_PARAM quadspi_conf = {

  0,                      /* DQS LoopBack */

  0,                      /* Reserved 1*/

  0,                      /* Reserved 2*/

  0,                      /* Reserved 3*/

  0,                      /* Reserved 4*/

  0,                      /* cs_hold_time */

  0,                      /* cs_setup_time */

  0x1000000,              /* A1 flash size */

  0,                      /* A2 flash size */

  0x1000000,              /* B1 flash size */

  0,                      /* B2 flash size */

  1,                      /* SCLK Freq - 60Mhz*/

  0,                      /* Reserved 5*/

  4,                      /* Quad Mode Flash */

  0,                      /* Port - Only A1 */

  0,                      /* DDR Mode Disable */

  0,                      /* DQS Disable */

  0,                      /* Parallel Mode Disable */

  0,                      /* Port A CS1 */

  0,                      /* Port B CS1 */

  0,                      /* FS Phase */

  0,                      /* FS Delay */

  0,                      /* DDR Sampling */

  /* LUT Programming */

  /* Quad read*/

  0x046B,

  0x0818,

  0x0C08,

  0x1E80,

  0x2400,

  0x0000

};

[abdulnihad]

Juan,

Now I am porting all my code which is working in vybrid tower system to custom vybrid platform with part number PVF522R3K1CMK4. we have interfaced spansion QSPI flash (FL128SA1F00) to QSPI0_A ( PTD0, 1, 2, 3, 4, 5) by referring vybrid tower system. I have verified hardware by using test code which will write and read QSPI flash. it is working fine. But I am not able to boot from QSPI.

I am using same config as explained in this thread...Could you please tell me what I am missing here while poring my code.

Also let me know, does PVF522R3K1CMK4 by default have an QSPI boot option?. Or do i need to do some fuse settings?. We also provided boot config jumpers to switch between different boot mode.

BR/-

nihad

[juangutierrez]

What I can assure is that this part does not have L2 Cache. Could that might be a problem?

Have you tried flashing a simple image (that just turn a led on) just to make sure it boots or not?

[juangutierrez]

Try to disable the L2 Cache by adding next line at $MQX_INSTALL_PATH/config/<board_name>/user_config.h,

#define PSP_HAS_L2_CACHE 0

and see if it helps, maybe you can try first to check if still working on TWR and then try it on PVF522R3K1CMK4.

[abdulnihad]

Hi,

I disabled L2 cache and flashed in TWR. It is booting. But when I flash in custom board it is not booting. I am using only one QSPI flash (FL128SA1F00) chip. DO I need to do any modification in LUT?. DO I need to do any eFuse settings in vybrid PVF522R3K1CMK4. I am attaching my scatter and qspi_boot.c file.

BR/-

Nihad

[juangutierrez]

As far as I know there is no extra eFuse setting to be done. But let me investigate.

I think the LUT in the quadspi_conf should be fine.

Not sure what can be wrong :smileysad:. Let me investigate

[juangutierrez]

Are you able to boot from a different device (like SD) with this part, or how were you able to flash the QSPI?

Also make sure you are setting the

BOOT_MODE [1:0] = 10 to boot from RCON

BOOT Device Selection

BOOT_CFG1[7:4] = 0000  (QSPI Serial Flash Memory)

BOOT_CFG1[1] = 0 – QuadSPI0 selected ( or 1 – QuadSPI1 selected)

Check the Mapping of the BOOT_CFG with its corresponding Pads at Table 19-3. GPIO Override Contact Assignments

[abdulnihad]

Hi,

I have checked the boot config pin..It is fine configured for QSPI0.

I never tried to boot from SD card.

I am usingDS-5 and DSTREAM jtag to load the quadspi_load project which intern flash the QSPI. I Can see that it is flashing without error. but when I change the to boot from quadspi, it is not booting.

BR/-

Nihad

[juangutierrez]

Try to just connect your JTAG (without loading) when booting from QSPI and inspect the QSPI memory (0x20000000)

Are you able to see the contents correctly?

This might be tricky too. At the very beginning, when A5 is taken out of reset, this memory will be inaccessible (it will show All 0x0 or All 0xff), but then at some point ROM will read the RCON pin and it will enable this memory. At this point you can check if the content is the expected. The quadspi_conf should be at 0x20000000 and the ivt information at 0x20000400.

Also you can try to add a watchpoint at the 0x20000400, so the ROM execution will break when reading the IVT, at this point ROM will be copying the contents of the QSPI to IRAM (0x3f000000).

It can be hard to debug without the ROM source code, but at least we can check firstly if the QSPI has been flashed correctly and then if ROM is copying the contents to IRAM.

[abdulnihad]

Hi,

I have configured the jumpers to boot from QSPI flash and powered up the board. Then I connected jtag using connect only option while board running. I got below message. it is always stopping at address 0x00002D24 whenever i tried to pause the debug. 0x20000000 shows always 0.

Connected to running target Freescale - Vybrid VF6xx on USB:003604

cd "C:\Users\abdulnihad\Documents\DS-5 Workspace"

Working directory "C:\Users\abdulnihad\Documents\DS-5 Workspace"

interrupt

Execution stopped at: S:0x00002D24

S:0x00002D24   LDR      r0,[r6,#4]

wait

continue

interrupt

Execution stopped at: S:0x00002D24

S:0x00002D24   LDR      r0,[r6,#4]

I have flashed my application using Quadspi_load project and read the flashed data using another test application. I can see what ever I have written in QSPI flash. Please find the attached file which contain data read from 0x20000000, 0x20000400, 0x20000800

[juangutierrez]

Memory looks fine

Regarding the LUT. Instructions are for using only one pad. Check that the QOR(6B) command is supported by your QSPI.

/* LUT Programming */

  /* Quad read*/

  0x046B, // quad read out command (using only one PAD/Line)

  0x0818, // 24 bit addresses (using only one PAD/Line)

Check the command 6B is supported by your QSPI memory. It should be QOR (Read Quad Out 3-4byte addr)

  0x0C08, // 8 dummy cycles (using only one PAD/Line)

  0x1E80, // read 128 bytes (using only one PAD/Line)

  0x2400, // Jump to Instruction 0

  0x0000 // END

I don't think this might be the problem (unless 6B is not supported in your memory) but you can try other sequences, Check 30.8.1 Example Sequences in RM.

After you connect and stuck in 0x00002D24. Try to do a system reset from the IDE, so Core will be executing code from address 0x0. Try to check how far it goes if possible. Is always end up stuck at 0x2d24. It is supposed that at some point will read the quadspi_conf, try to add (if possible) a watchpoint there.

[juangutierrez]

Also, could you post the contents of SRC_SBMR1(4006_E004h) and SRC_SBMR2(4006_E01Ch) registers.

This will give us the fuse and Pin config settings.

Also change your pin settings and see if those changes are reflected in those two registers.

[abdulnihad]

Hi,

I have attached data sheet of flash. part number used is FL128SAIF00.

As you said I have captured register values given below.

SRC_SBMR1    0x9FCBBF05    32    RO

  BOOT_CFG1    0b00000101    8    RO

  BOOT_CFG2    0b10111111    8    RO

  BOOT_CFG3    0b11001011    8    RO

  BOOT_CFG4    0b10011111    8    RO

SRC_SRSR    0x00FEFF65    32    R/W

SRC_SECR    0x00000000    32    R/W

SRC_GPSR    0x00000000    32    RO

SRC_SICR    0xFF000002    32    R/W

SRC_SIMR    0x00FFFFFD    32    R/W

SRC_SBMR2    0xEA000000    32    RO

  SEC_CONFIG    0b00    2    RO

  DIR_BT_DIS    0b0    1    RO

  BT_FUSE_SEL    0b0    1    RO

  BMOD    0b10    2    RO

Also attached command log captured from DS-5 command window during step after reset using JTAG (logJtagReset).

I have put watch point at 0x20000000 and 0x20000400, It never hits..

BR/-

nihad

[kef2]

BOOT_CFG4

0b10011111

8

RO

It seems RCON31 / PTB2 is high, which is "Infinite loop"=Enable. Boot ROM doesn't boot with this setting and waits until you tell GO in debugger.

[abdulnihad]

Hi,

If it goes to infinite loop. then even UART0 and SD card boot also not work. am I right?. below gives the RCON mapping in our target platform. Is there any work around to pull RCON31 low.

PTE7  RCON0 BOOT_CFG1[0]  = floating

PTE8  RCON1 BOOT_CFG1[1]  = used as RCON1

PTE9  RCON2 BOOT_CFG1[2]  = floating

PTE10 RCON3 BOOT_CFG1[3]  = used as RCON3

PTE11 RCON4 BOOT_CFG1[4]  = used as RCON4

PTE12 RCON5 BOOT_CFG1[5]  = used as RCON5

PTE15 RCON6 BOOT_CFG1[6]  = used as RCON6

PTE16 RCON7 BOOT_CFG1[7]  = used as RCON7

PTE17 RCON8 BOOT_CFG2[0]  = floating

PTE18 RCON9 BOOT_CFG2[1]  = floating

PTE19 RCON10 BOOT_CFG2[2] = floating

PTE20 RCON11 BOOT_CFG2[3] = used as RCON11

PTE23 RCON12 BOOT_CFG2[4] = floating

PTE24 RCON13 BOOT_CFG2[5] = used as RCON13

PTE25 RCON14 BOOT_CFG2[6] = floating

PTE26 RCON15 BOOT_CFG2[7] = floating

PTE27 RCON16 BOOT_CFG3[0] = floating

PTE28 RCON17 BOOT_CFG3[1] = floating

PTC0  RCON18 BOOT_CFG3[2] = used as MDC

PTC1  RCON19 BOOT_CFG3[3] = used as MDIO

PTC2  RCON20 BOOT_CFG3[4] = used as CRS_DV

PTB26 RCON21 BOOT_CFG3[5] = used as RCON21

PTB27 RCON22 BOOT_CFG3[6] = floating

PTB28 RCON23 BOOT_CFG3[7] = floating

PTC26 RCON24 BOOT_CFG4[0] = floating

PTC27 RCON25 BOOT_CFG4[1] = floating

PTC28 RCON26 BOOT_CFG4[2] = floating

PTC29 RCON27 BOOT_CFG4[3] = floating

PTC30 RCON28 BOOT_CFG4[4] = floating

PTC31 RCON29 BOOT_CFG4[5] = floating

PTB1  RCON30 BOOT_CFG4[6] = Used as SAI2_RX_DATA

PTB2  RCON31 BOOT_CFG4[7] = floating

BR/-

Nihad

[kef2]

Abdul,

Looks like you need to use BT_FUSE_SEL fuse = 1, which will force boot from fuses.and ignore RCON pins. You need to program OTP fuses properly. Mistake in fuse config will brick Vybrid :-(.

[abdulnihad]

Hi,

Could you please tell me how to program OTP fuses. Let me know what need to be done for QSPI boot.

I migrated my application to MQX4.1 from MQX4.0.2...., Now I am not able to boot my application from QSPI flash in vybrid tower. size of my MQX4.0.2 application flashed in QSPI is 129KB. and size of my MQX4.1 application is 160KB.

BR/-

Nihad