MQX Interrupt Shared Peripheral Routing

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MQX Interrupt Shared Peripheral Routing

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carlovalgocela
Contributor III

Reading the Vybrid AN4947.pdf,  and in 4.2 Dual-core communication and synchronization options,

• Interrupts. Routing options for both cores — none, one, or both cores can be notified for the event.

I wanted for  M4 MQX NVIC Interrupt 10 and 11 not to be shared on the A5 Linux.

I use this code to configure the routing.

/* Disable shared interrupt to A5 Core */

    _irouter_routing(26,0,0);

    _irouter_routing(27,0,0);

However it is not working. A5 Linux could still received and processed the interrupts.

Any ideas what I missed?

interrupt.png

I'm using MQX Version 4.1.1

Thanks,

Carlo Val

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karina_valencia
NXP Apps Support
NXP Apps Support

alejandrolozano​ are you able to help here?

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alejandrolozan1
NXP Employee
NXP Employee

Hi,

I'd like to reproduce the behavior first. Carlo, which Linux BSP are you using?

Best Regards,

Alejandro

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carlovalgocela
Contributor III

I'm using Linux version 3.0.15-ts-armv7l .

I saw yesterday in a file init_gic.c  routing all interrupts to Core 1.

Ill try it today and see if it will work

Here is my update would be:

volatile uint16_t *ptr26;

volatile uint16_t *ptr27;

ptr26 = &MSCM_IRSPRC26;

*ptr26 = MSCM_IRSPRC_CP1En_MASK; /* route interrupts to core 1*/

ptr27 = &MSCM_IRSPRC27;

*ptr27 = MSCM_IRSPRC_CP1En_MASK; /* route interrupts to core 1*/

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alejandrolozan1
NXP Employee
NXP Employee

Hi Carlo,

Did you modification work?

Regards,

Alejandro

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carlovalgocela
Contributor III

Hello alejandrolozano​,

No it didn't work :-(

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alejandrolozan1
NXP Employee
NXP Employee

Hi,

On Linux side you could try to disable the interrupt routed to the A5 corresponding to the DMA.

void mvf_init_irq(void)

{

        unsigned int i;

        void __iomem *int_router_base =

                                MVF_IO_ADDRESS(MVF_MSCM_INT_ROUTER_BASE);

        struct irq_desc *desc;

        unsigned short route;

        /* start offset if private timer irq id, which is 29.

         * ID table:

         * Global timer, PPI -> ID27

         * A legacy nFIQ, PPI -> ID28

         * Private timer, PPI -> ID29

         * Watchdog timers, PPI -> ID30

         * A legacy nIRQ, PPI -> ID31

         */

        gic_init(0, 27, MVF_IO_ADDRESS(MVF_INTD_BASE_ADDR),

                MVF_IO_ADDRESS(MVF_SCUGIC_BASE_ADDR + 0x100));

        for (i = MXC_INT_START; i <= MXC_INT_END; i++) {

                desc = irq_to_desc(i);

                desc->irq_data.chip->irq_set_wake = mvf_gic_irq_set_wake;

        }

        mvf_register_gpios();

        int_router_base += 0x80;

        for (i = 0; i < 112; i++) {

                route = 1 | __raw_readw(int_router_base);

                __raw_writew(route, int_router_base);

                int_router_base += 2;

        }

}

This function is found at vim arch/arm/mach-mvf/irq.c

Let me debug the M4 (MQX side) to verify the possible problem.

Best Regards,

Alejandro

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alejandrolozan1
NXP Employee
NXP Employee

Hi Carlo,

Did you try the previous suggestion?

Best Regards,

Alejandro

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