LPDDR2 Configuration

[jonpartee]

What do the TINIT, TINIT3, TINIT4, TINIT5 in the DDR_CR02-DDR_CR05 Correspond to in reference to LPDDR2 data sheet.  The latest reference manual has little/no information on this.  Not all of the LPDDR2 datasheets label the INIT times the same.

Jon

[ioseph_martinez · Accepted solution]

Yes, seems the manual is lacking from that information.

TINIT: Defines the DRAM initialization delay, in memory clocks.(time required for memory clocks to be started and stabilized before clock enable becomes active)

TINIT3: Defines the number of memory clocks required from CKE assertion to memory reset. (this parameter only applies when the controller is configured for LPDDR2)

TINIT4: Defines the number of memory clocks required from memory reset to an MRR command (this parameter only applies when the controller is configured for LPDDR2)

TINIT5: Defines the maximum number of memory clocks required from memory reset to initialization complete (this parameter only applies when the controller is configured for LPDDR2)

AlejandroSierra, you may be interested on this...