DDR3 CR154 Setting

[tomokiokuno]

Dear Forum members,

I would like to know about DDRMC_CR154 Register.

A discussions here about DDRMC_CR154 Register exists as follows;

• Bring up DDR3 Memory on Vybrid (No.383998)
• DDR3 Intermittent Problem (No.372438)

In those discussion, Forum members recommend DDRMC_CR154 change from 0x68200000

to 0x682C0000.In other words DDR_SEL_PAD_Control bit change to DDR3 mode.

We use DDR3 SDRAM on Vybrid VF6 Board.

What electrical characteristic chenges when we change Bit19-18(DDR_SEL_PAD_Control) in CR154?

I hope your reply, for example

• DQ wave pattern changes.
• This affects both cold boot and warm boot.
• After RESET# is de-asserted, Timing of CKE becomes active is chenged.
• etc...

In Reference BSP, DDR_SEL_PAD_Control was set in 00b.

What problem occurs when we use this setting in Si 1.1?

I would like you to tell me more about that in detail.

Regards,

Tomoki

[RossMcLuckie]

This is to do with a dependency between hardware and software calibration in 1.0 silicon, one could lock out the other and prevent calibration completing successfully, workaround was to set DDR_CLASS to 0, from silicon 1.1 onwards this dependency was removed and they are independent now, DDR_CLASS can be set to 11 for DDR3, as it was intended.

Ross

[tomokiokuno]

Dear Ross,

Thank you for the reply. That means, Dose DDR_CLASS bit enable the hardware PAD calibration?

I would like to ask you the following questions;

• Which setting of PAD_ZQ_MODE(bit22-21 in CR154) is the best 0x0 or 0x1 or 0x2?
• Dose Wave pattern of ddr_data/address/dq PAD change by chenge of DDR_CLASS in Si 1.1?
• Dose DDR access become unstable if we do not make DDR_CLASS=11b in Si 1.1?

We cannot change it easily...

Because our several evaluations was complete in the state of DDR_CLASS=00b.

I want to know what kind of influence that has.

Regards,

Tomoki

[RossMcLuckie · Accepted solution]

Hi Tomoki,

Essentially we have separated the ZQ and other pad calibration controls, on 1.0 silicon they were linked and one could lock out the other, the workaround was setting DDR_CLASS to 0, however this is technically a reserved state and should not be used, only 0x11 for DDR3 or 0x10 for LPDDR2, if you continue to use 0x00, this is out of spec and we will consider that so should you see any problems, and a value of 0x00 will not be supported by Freescale.

There is no need to change any other values, for PAD_ZQ_MODE we use 0x1, which performs calibration the most, whether you want to try the other values is up to you, dependent on your layout, mode of operation, etc.

Board layout is also a big factor here, so regards stability it is hard to know exactly, board dependent, from our own experience we have two reference boards, the TWR board (rev G) did not seem susceptible to this change and 1.1 silicon continued to work with a 0 setting, however our other platform failed on every power on, recently we have updated our TWR to rev H, the DDR layout has completely changed, we are using a T layout with no external termination and it now fails ever power on with the 0 setting and has no issues with 0x11, and our stress testing shows the DDR performance of rev H to be better than rev G.

This is just some background for you, in summary if you do not make the change to 0x11, then you are operating the part out of spec and we would not guarantee the part operating in that condition.

Ross

[tomokiokuno]

Dear Ross,

Thank you for the detailed explanation, we intend to re-evaluate by DDR_CLASS=11b setting.

There is one final favor I would like to ask of you.
You wrote it as follows;
>we are using a T layout with no external termination and it now
>fails ever power on with the 0 setting and has no issues with 0x11,
Why did you remake rev H board without external terminal?
Probably it is Center-Tap Terminated of 47ohm.
Should we make the same as it?

Regards,
Tomoki

[RossMcLuckie]

Hi Tomoki,

There is no hard requirement for you to change your DRAM layout. Essentially we now have two approaches we can take, the more traditional fly-by, which requires external termination resistors, typically a more robust design, easier to get working, more tolerant to layout deviations, but adds cost in BOM (R's) and power consumption.

The T layout approach is more difficult to get working, layout rules have to be precisely followed, less likely to work with poor layout, but you save on BOM cost and have a reduction in power.

We often get asked to provide a T style reference layout for customers to use, as this is the more difficult to get right, fly-by is the more common approach and easier to get to work, so it makes more sense for us to use the T methodology when we can.

This is entirely customer choice, both approaches will work and have their own pros and cons.

Ross

[tomokiokuno]

Dear Ross,

Please tell me in a little bit more detail about that.

1. You wrote "other pad calibration controls", Specifically, what pad is "other pad"? (for example, DQ, DQS...)
2. Even in case of fly-by approach with external termination resistors, may I use DDR_CLASS=11b setting?
3. In Reference Manual Rev5, it is written that DDR_SEL_ZQ_PAD_Contr(bit17-16 in CR 154) should be set to 00b, in both DDR3 mode and LPDDR2 mode. Which is right?
4. I think T layout is approach in case of plural SDRAM, Were you going to connect plural SDRAM in Rev H board? (we use only one SDRAM with our board.)

Thank you for your time.

Regards,

Tomoki

[RossMcLuckie]

Hi Tomoki,

For 1, apologies I wasn't very clear, the separation of controls refers to the hardware and software ZQ calibration modes, before the fix one could lock out the other, they are now independent of each other and there is no risk of locking up calibration.

For 2, you must set DDR_CLASS to the specified value for the memory in use (DDR3 or LPDDR2), otherwise you are operating out of spec, this is independent of the layout methodology in use

For 3, in not really sure the background of these bits, whether they are redundant or just have no real impact, but the value 00 for either memory is correct and what should be used.

For 4, We have DRAM's on the TWR board and yes there are limitations to what you should use T layout for. This is not Freescale specific, there are many application notes and white papers on this, especially from the DRAM suppliers themselves, if you wish to research this further I recommend you start there.

Regards

Ross

[tomokiokuno]

Thank you for your support!

[Wlodek_D_]

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