Can 2 RMII_CLKOUTs output at the same time?

[Hiroki]

Hi team,

Can user select 2pins as RMII_CLKOUTs at the same time and connect Ether PHYs with each pins?

If possible, what output delay time is there between each pins?

And, my understanding is the RMII_CLKOUT is PLL5 clk output signal. Is it correct?

Best Regards,

Hiroki

[naoumgitnik]

Dear Hiroki,

1. May you provide additional clarification, please? - What is the reason for this question - having more than one Ethernet PHY? If so, do they share the same RMII interface lines but have separate "Chip Select" lines?
2. As per the RMII specification, the CLKOUT signal is used to sample data in both RX and TX directions. According to the preliminary Vybrid Reference Manual, "Both TX and RX clock in RMII mode are muxed into one signal. The source can be either PAD_0-ALT2 /  PAD2-ALT3 / PLL5 main clock / Audio Ext clock as explained in Section 9.10.6 Ethernet RMII Clocking."

Sincerely, Naoum Gitnik.

[Hiroki]

Hi Naoum,

Mitsubishi is planning to produce an integrated control system of industrial air-conditioner. They want to use 2 ethernet devices concurrently. They connect Vybrid with 2 ethernet PHYs. So they confirm whethever Vybrid can provide RMII_CLKOUT to 2 external ethernet PHYs concurrently or not and then RMII_CLKOUT pins have delay or not.

And they are planning to use PLL5 as RMII clock source. Then does RMII_CLKOUT output PLL5 clock?

Best Regards,

Hiroki

[naoumgitnik · Accepted solution]

Dear Hiroki,

1. You may configure Vybrid to have the same RMII_CLKOUT signal on both PTA6 and PTA9 balls (see IOMUX Registers for these balls), and for the 50MHz RMII_CLKOUT signal their timing differences (caused by using different physical paths inside the chip) are negligible. At the same time, why not use only one RMII_CLKOUT output ball for both Ethernet PHYs? Their high-impedance CMOS inputs would not overload the Vybrid's output. If the 2 PHYs are placed close to each other, bring RMII_CLKOUT to their vicinity, then split the line, so that the short stubs (actually signal reflections due to their presence) created by that "fork" do not distort the signal.
2. RMII_CLKOUT is either 'PLL5 main clock' or 'Divided by 2 of PLL5 main clock'.

Sincerely, Naoum Gitnik.