8-bit NAND interface

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8-bit NAND interface

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mnw
Contributor II

We have an 8-bit NAND part on a board and can't get an ID out of it.  The NAND part is the 8-bit version of the one on the tower board.  The only code change that I can see we need to do is ensure the BITWIDTH bit in the NFC_CFG register is not set.

Does anyone else have an experience with this?

Thanks.

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ioseph_martinez
NXP Employee
NXP Employee

I got this info from a colleague, is how to use the one on the Tower board as a 8bit NAND:

Steps to get TWR-VF600 16-bit to work on 8-bit:

  1. 1. IOMUX for NAND IO, set up  only 0-7. Command will set to lower byte, if send to high byte. The NAND device will not recognize any command send by the controller.
  2. 2. NAND_CFG, set to 8-bit for erase/program/read
  3. 3. Spare bytes reduce to 32-bytes instead of 64-bytes; therefore, your HW ECC should set to 24-byte ECC.

What happen here is that 128MB of flash will be half of the size, the other half will not be used. When the controller read/write, it will be lower half of the byte.

Comparing to what you are doing, I think would be good to check the following:

- can you try this on the tower board?

- is the NAND connected on your board to the lower lines? 0-7

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ioseph_martinez
NXP Employee
NXP Employee

I don't have experience on NAND but found this thread on this community https://community.freescale.com/thread/265412

Perhaps if you look at the i.mx53 sw as reference it may help.

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mnw
Contributor II

Thanks Ioseph.

We have implemented NAND (in 8-bit mode) on an i.MX53 design.  Unfortunately the NFC controller in Vybrid is quite different to the 53. 

I'm sure it is something we are doing wrong, but it would be nice to know that Freescale (or someone else) has had it going in 8-bit mode.

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ioseph_martinez
NXP Employee
NXP Employee

I got this info from a colleague, is how to use the one on the Tower board as a 8bit NAND:

Steps to get TWR-VF600 16-bit to work on 8-bit:

  1. 1. IOMUX for NAND IO, set up  only 0-7. Command will set to lower byte, if send to high byte. The NAND device will not recognize any command send by the controller.
  2. 2. NAND_CFG, set to 8-bit for erase/program/read
  3. 3. Spare bytes reduce to 32-bytes instead of 64-bytes; therefore, your HW ECC should set to 24-byte ECC.

What happen here is that 128MB of flash will be half of the size, the other half will not be used. When the controller read/write, it will be lower half of the byte.

Comparing to what you are doing, I think would be good to check the following:

- can you try this on the tower board?

- is the NAND connected on your board to the lower lines? 0-7

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mnw
Contributor II

Thanks.

I did not try this, but was able to get the flash part responding to the ID command using the latest MQX beta.

The whole test is not working, but there may be other software reasons for that.  I do have a couple of questions about some strange things I'm seeing:

1. The MQX and u-Boot code is very different when comparing how the I/O lines are setup. u-Boot enables both the input and output buffer (OBE and IBE bits),but MQX only enables IBE.  Do you have any comments or recommendations on which software to follow?

2. When analysing the ID Read sequence,  I see the CE# line cycle for every bus cycle.  The timing diagram for the Micron NAND shows that CE# should stay low for the whole operation.  Is there a setting in the controller to fix this?

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ioseph_martinez
NXP Employee
NXP Employee

Hi Martin,

Maybe better if you post a this questions on a different thread?

Since the topic is a bit different now...

Thanks,

Ioseph

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ioseph_martinez
NXP Employee
NXP Employee

You are right, the NFC in Vybrid is different from the i.MX family. I actually reviewed some material and seems to be the same controller used on Kinetis family. So let me check internally who with some experience on it can help.

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