32-Bit DMA Transfer Not Correctly Functioning

[nathanb_]

Hello All,

I'm currently trying to do a DMA transfer into an eDMA register related to an SPI transfer and it does not seem to be correctly working for some reason.  This is on a Vybrid VF6XX processor.

If I manually do:

//DMA30_EEI, DMA30_CEEI, DMA30_CERQ = ignore,  DMA30_SERQ = enable SPI DMA

*(uint32_t*)0x40098018 = (30<<24) + 0x808080;

Then the SPI launches no problem

If I use another DMA channel to transfer the memory into 0x40098018, the SPI does not start.

uint32_t test[1];

test[0] = (30<<24) + 0x808080;

transferDescriptor.SRC_ADDR  = (uint32_t)((uint32_t *)&(test[0]));

transferDescriptor.DST_ADDR  = (uint32_t) (0x40098018);

transferDescriptor.SRC_WIDTH = 4;

transferDescriptor.SRC_MODULO = 0;

transferDescriptor.SRC_OFFSET = 0;

transferDescriptor.DST_MODULO = 0;

transferDescriptor.DST_OFFSET = 0;

transferDescriptor.DST_WIDTH = 4;

transferDescriptor.LOOP_BYTES = 4;

transferDescriptor.LOOP_COUNT = 1;

transferDescriptor.LOOP_SRC_OFFSET = 0;

transferDescriptor.LOOP_DST_OFFSET = 0;

dma_request_enable(transferChannel);

dma_transfer_submit(transferChannel, &transferDescriptor, NULL);

If I use the same DMA channel and do an 8-bit transfer instead of 32-bit transfer, the SPI DOES start.

uint8_t test[1];

test[0] = (30);

transferDescriptor.SRC_ADDR  = (uint32_t)((uint32_t *)&(test[0]));

transferDescriptor.DST_ADDR  = (uint32_t) (0x4009801b);

transferDescriptor.SRC_WIDTH = 1;

transferDescriptor.SRC_MODULO = 0;

transferDescriptor.SRC_OFFSET = 0;

transferDescriptor.DST_MODULO = 0;

transferDescriptor.DST_OFFSET = 0;

transferDescriptor.DST_WIDTH = 1;

transferDescriptor.LOOP_BYTES = 1;

transferDescriptor.LOOP_COUNT = 1;

transferDescriptor.LOOP_SRC_OFFSET = 0;

transferDescriptor.LOOP_DST_OFFSET = 0;

dma_request_enable(transferChannel);

dma_transfer_submit(transferChannel, &transferDescriptor, NULL);

Does anyone know what's going on here?  I need to be able to do this with a 32-bit DMA transfer instead of an 8-bit DMA transfer, so that I can also modify another 32-bit register with an incremented offset.

Thanks everyone.

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[timesyssupport]

Hello Nathan,

Is this issue being encountered when running Linux, or MQX? Or, is MQX running alongside MQX?

Regards,

Timesys Support

[nathanb_]

Hello Timesys,

Linux is running on the A5

MQX is running on the M4

MQX is setting up and running the DMA transfer

The issue occurs whether or not Linux is running (if I sit in u-boot, the same thing happens)

Thanks,

Nathan

[alejandrolozan1]

Hi,

Just to clarify, you are trying to modify the configuration of a DMA module with a DMA transfer from a different one, correct?

I wonder if just linking channels or the scatter gather feature may help. Is there a restriction to use that?

Best Regards,

Alejandro

[nathanb_]

Alejandro,

You are correct.  Yes I am trying to modify the config of a DMA module with a DMA transfer from a different module.

Linking channels with an 8-bit transfer and a 32-bit transfer would work for us, I think.  I don't believe we have any restrictions.  We just need a way to set DMAx_TCDn_DADDR and DMAx_SERQ from another DMAy transfer.

Thanks again.

[alejandrolozan1]

Hi,

We have examples for scatter-gather and channel linking for other architectures. Please refer to the attached examples. The DMA module and DMA MUX is quite similar and it should be very easy to migrate the configuration to Vybrid.

I hope it helps,

Alejandro

[nathanb_]

I am using an interrupt to do it at the moment now.  I will investigate moving it to a channel linked DMA when I get a chance.

Thanks.

[karina_valencia]

timesyssupport​ are you able to help here?