T4240 CoreNet partitioning

[bobperry]

I am trying to establish partitioning of the L3 cache to isolate certain cores owing to over usage of the cache by other cores.  Looking at the EREF the level 2 cache is controlled by the PIR register but the T4240 reference manual says the L3 is controlled by the PID register.  Should this not be the PIR register.

Also, the PIR register does not appear to be setup in accordance with the reference manual.  All the thread 1's have correct values in the PIR register but thread 0 is incorrect ie.

core 17 PIR=0x41

core 18 PIR=0x12

core 19 PIR=0x49

core 20 PIR=0x20

core 21 PIR=0x51

....

Does anyone have code showing how to partition both L2 and L3 cache?

[yipingwang]

Hello Bob Perry,

For L2 Cache partitioning, please refer to sections "5.8.4.5 L2 cache partitioning" and "2.12.4 L2 cache partitioning registers" in https://www.nxp.com/docs/en/reference-manual/E6500RM.pdf.

CPC(L3 cache) cannot be programmed to be partitioned by way of cores/CPU(sources). You can only partition the CPC by way of transactions based on addresses usually using hypervisor.

A key aspect of partitioning a system is to partition the system's physical memory. To do this physical memory is divided into physical memory areas (or PMAs). PMAs are statically defined by the system architect and cannot be changed dynamically in a running system. The hypervisor itself is also assigned a PMA for its internal use.

A PMA is defined with the following properties:

    True physical address (must be size aligned)

    Size (must be a power of 2)

CPC partitioning—specifies one or more ways of the Corenet platform cache (CPC) to be allocated and dedicated to this PMA.

Each PMA corresponds to a CoreNet coherence domain (CSDID). Coherence is implied—if a PMA is only referenced by one partition, the PMA is private to that partition and only CPUs within that partition are snooped to maintain cache coherency. For shared PMAs, all partitions that reference the PMA will have their CPUs listed in the CSDID for the PMA.

Have a great day,
TIC

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[bobperry]

Hi Yiping Wang,

Many thanks for your reply.  I have been reading this same very subject on the PMA.

I am running baremetal so no hypervisor not that this should make the setup any more difficult.

How are the PMA's statically defined?  I can see them in Codewarrior (1 thru 16) and as they are memory addressable I assume that they can be changed?

How do CPUs belong to a partition?

You mention CPC partitioning too.  Are there other documents that clarify this in more detail and how to establish L3 cache separation between cores?

Many thanks

Bob

[bobperry]

Is it controlled by the device tree entry of :

fsl,portid-mapping

[bobperry]

I have followed the T4240 reference manual where it says to:

1. Clear all bits of CPCPARn (this prevents any new transactions from allocating into
the CPC) using write operation. - Doing this hangs the CPU and CodeWarrior
2. Flush the CPC using one of the two following methods:
• Harware flush: Set CPCCSR0[CPCFL] and wait for hardware to clear
CPCCSR0[CPCFL] by polling - I have implemented this stage.
• Software flush: perform a dcbf operation to each coherency granule mapped to
the memory target (that is, one dcbf for each 64 bytes).
3. Clear all lock bits by setting CPCCSR0[CPCLFC].
4. Wait for hardware to clear CPCCSR0[CPCLFC] using a polling loop.
5. Disable the CPC by clearing CPCCSR0[CPCE].
6. Reconfigure CPC as desired.
7. Enable CPC by setting CPCCSR0[CPCE].

However, doing anything with the PAR register hangs both CodeWarrior and also the processor.  Removing that step the registers update correctly.  The issue I then have is that when the kernel commences to load the CPU hangs in the decompression stage.  If I do the above using some UBoot scripting it works.  Do not understand.

The biggest concern I have though is over the content of the PIR register.  It just is not behaving properly.

The other issue is understanding what is used by the system to coordinate the CPCPIRn registers.