T2080RDB-PCIe debug error!

[jiachaozhang]

T2080RDB-PCIe Debug error. Failed cfg JTAG chain, cann't into debuger with usb TAP.ufedor

[ufedor]

Assuming that the board is not factory new please explain how the problem state was achieved.

[jiachaozhang]

    I supply JTAG config for you,

    please Look up, thinks a lot !  

[ufedor]

There could be several reasons for such behaviour.

One of them is absent/damaged RCW.

Please explain how the problem state was achieved.

Is the board factory new?

[jiachaozhang]

          uboot can boot , then rcw is ok

          how do i to recovery factory state ? 

[ufedor]

> uboot can boot , then rcw is ok

Please provide complete U-Boot booting log as text file.

[jiachaozhang]

this is the uboot booting log :

U-Boot 2016.012.0+ga9b437f (May 15 2016 - 10:38:22 +0800)

CPU0: T2080E, Version: 1.1, (0x85380011)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1799.820 MHz, CPU1:1799.820 MHz, CPU2:1799.820 MHz, CPU3:1799.820 MHz,
CCB:599.940 MHz,
DDR:933.310 MHz (1866.620 MT/s data rate) (Asynchronous), IFC:149.985 MHz
FMAN1: 699.930 MHz
QMAN: 299.970 MHz
PME: 599.940 MHz
L1: D-cache 32 KiB enabled
I-cache 32 KiB enabled
Reset Configuration Word (RCW):
00000000: 1207001b 15000000 00000000 00000000
00000010: 66150002 00000000 ec027000 c1000000
00000020: 00800000 00000000 00000000 000307fc
00000030: 00000000 00000000 00000000 00000004
I2C: ready
Board: T2080RDB, Board rev: 0x01 CPLD ver: 0x06, boot from NOR vBank1
SERDES Reference Clocks:
SD1_CLK1=156.25MHZ, SD1_CLK2=100.00MHZ
SD2_CLK1=100.00MHZ, SD2_CLK2=100.00MHZ
SPI: ready
DRAM: Initializing....using SPD
Detected UDIMM D3XP56082XL10AA
2 GiB left unmapped
4 GiB (DDR3, 64-bit, CL=13, ECC on)
DDR Chip-Select Interleaving Mode: CS0+CS1
VID: Core voltage after adjustment is at 1023 mV
Flash: 128 MiB
L2: 2 MiB enabled
Corenet Platform Cache: 512 KiB enabled
Using SERDES1 Protocol: 102 (0x66)
Using SERDES2 Protocol: 21 (0x15)
SEC0: RNG instantiated
NAND: 512 MiB
MMC: FSL_SDHC: 0
EEPROM: Invalid ID (ff ff ff ff)
PCIe1: Endpoint, undetermined, regs @ 0xfe240000
PCIe1: Bus 00 - 00
PCIe2: Root Complex, x2 gen2, regs @ 0xfe250000
02:00.0 - 1957:0808 - Processor
PCIe2: Bus 01 - 02
PCIe3: disabled
PCIe4: Root Complex, no link, regs @ 0xfe270000
PCIe4: Bus 03 - 03
In: serial
Out: serial
Err: serial
Net: Fman1: Uploading microcode version 106.4.18
FM1@DTSEC3 [PRIME], FM1@DTSEC4
Error: FM1@DTSEC4 address not set.
, FM1@TGEC1
Error: FM1@TGEC1 address not set.
, FM1@TGEC2
Error: FM1@TGEC2 address not set.
, FM1@TGEC3
Error: FM1@TGEC3 address not set.
, FM1@TGEC4
Error: FM1@TGEC4 address not set.

Hit any key to stop autoboot: 10     9     8     7     0

thinks a lot!

[jiachaozhang]

 >Please explain how the problem state was achieved.

First time,  I can connect T2080 using codewarrier usb tap to  debug my boot;

after a while,  I restart  codewarrier  debug,   

then I can not connect T2080  in any way 

[ufedor]

Please check connection integrity of all CodeWarrior TAP cables.

Detach and re-attach all cables from the CodeWarrior TAP and the T2080RDB JTAG/COP header (check that correct on-board header is used!).