T2080 SerDes Clock Signals

[paulagarcía-mor]

I am working with a T2080 device and I need some help to understand the voltage level of some signals.

According to the datasheet of the microprocessor, the input voltage range of every SerDes signal, including clocks, is GND to SVDD (which is 1V).

But, in the reference design board, the serdes clock signals that go to the T2080 inputs (SD1_REFCLK1_P, SD_REFCLK1_N...) have a higher voltage level (2V5/3V3).

How can it be possible?  Is the input voltage range higher for clock signals than for the rest of the serdes signals?

Thank you in advance.

Paula

[alexander_yakov]

According to the datasheet of the microprocessor, the input voltage range of every SerDes signal, including clocks, is GND to SVDD (which is 1V).

Please look T2080 device datasheet, Section 3.19.2.2 "SerDes reference clock receiver characteristics". There are 50 Ohm on-chip termination and AC decoupling. Actual voltage amplitude depends on how clock driver is coupled with clock input.

But, in the reference design board, the serdes clock signals that go to the T2080 inputs (SD1_REFCLK1_P, SD_REFCLK1_N...) have a higher voltage level (2V5/3V3).

The chip U23 (PI3PCIE3212), which is powered from 3.3V, is only switch chip, and the fact that this switch is powered from 3.3V does not mean output signals are 3.3V. The chip U48 (IDT9FGV0641) is powered from 1.8V, and there is also output termination.

Have a great day,
Alexander,
TIC

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