T1024 LBC Mapping Issue

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T1024 LBC Mapping Issue

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ramkrishnan
Contributor III

I am trying to map devices attached to the CS2 using GPCM in the DTS file. But it looks like the fsl_lbc.h file is mis-matched with the register addresses in the T1024 Reference Manual. 

In the DTB I mapped the fpga using 

fpga@2,0 {
compatible = "fsl,elbc-gpcm-uio";
reg = <0x2 0x0 0x100>;
elbc-gpcm-br = <0xa0000105>;
elbc-gpcm-or = <0x00000000>;

};

I am trying to map it to a uio for reading memory mapped registers. Range 2 is defined as 0xA0000000 and it is mapped to Chip Select 2. If I do a md.w on the uboot it works fine. 

But if I try to use the dtb to initialize the uio for this device it gives an error saying "fsl,elbc-gpcm-uio fa0000000.fpga: address mask / size mismatch" .  I checked the code and put in printk in various places and saw that the bitmasks and other field values in fsl_lbc.h is mismatched witht he T1024RM. For eg the BA in CSPR2 is defined as a 16 bit field but in the file it is defined as a 17 bit mask. The MSEL is defined as a 2 bit field in the T1024M at the 23rd bit offset while in the file it is defined as a 3 bit mask 0xE0.  I am using SDK 2.0 which is the latest one. Is this file outdated or am I looking at a wrong approach to memory mapped uio. 

These are from the fsl.lbc.h file. 

#define BR_BA 0xFFFF8000
#define BR_BA_SHIFT 15

Thank you,

Ram Krishnan

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ramkrishnan
Contributor III

Then would you be able to help me in figuring out how to memory map using uio and to define it in the dts. There was support for the p1022 generic-uio but that support is not there for the t1024.

Thank you,

Ram

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ramkrishnan
Contributor III

I have set the mask and entered the same information as br and the or information in the dts file. But when it comes up this error pops up where it says the mask/size is mismatched. But the only information that I give in the dts is the br and or. This does not contain the mask. Which leads me to believe that the file might be addressing another chipset with different definitions.

Ram

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alexander_yakov
NXP TechSupport
NXP TechSupport

Yes, your understanding is correct, T1024 processor does not have LBC, so this driver is not directly applicable.

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ramkrishnan
Contributor III

It is a 16 bit address line. There are 3 devices hanging off those line which I need to memory map. 

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alexander_yakov
NXP TechSupport
NXP TechSupport

If your device has only 16 address lines and data bus width is 8-bit, than the number of unique addressable cells in this device is 2^16 = 65536 cells, where one cell is equal to 1 byte.

For our processor each address always address one byte, regardless of bus width of connected device.

For 65536 bytes you need address space from 0 to 65535 or from 0 to 0xFFFF in hex.

In your case you have selected base address as 0xA0000000, this means that your device address space will be from 0xA0000000 to 0xA000FFFF. So, the only least 16 bits in address should be unmasked. In other words, correct address mask for your case is 0xFFFF0000.

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ramkrishnan
Contributor III

Thank you for the prompt response.

If I look  at section 23.3.7 Chip-Select Option register - GPCM (IFC_CSORn_GPCM) zero seems to be valid. If that is not the correct value , what should it be ? 

The AMASK2 is set to f0000000 which translates to 256M. But when looking at the fsl_lbc.h I see the bitmask definitions do not match the T1024 Reference Manual (eg being the BA mask which is set to FFFF8000 while the actual mask should be FFFF0000). Are they meant for another chip family. There is no indication of that though. 

Please let me know if you need any specific information and I will provide that.

Thanks,

Ram

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alexander_yakov
NXP TechSupport
NXP TechSupport

What is the actual size of your GPCM device - how many address lines you have physically connected to your device?

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alexander_yakov
NXP TechSupport
NXP TechSupport

Address mask/size mismatch means you have not defined the value of size, or have not set address mask defining the size of memory space you are assigning for your chip select. Looking to your OR/BR settings, I see OR register is defined to all zeros, this is obviously incorrect.


Have a great day,
Alexander

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