Is there any help or guidance for configuring the IFC GPCM for the T-series processors? The IFC appears much more configurable than previous series, and I am having some trouble working out the overall read and write cycle times and how they effect the connected devices; an FPGA in this case.
Thanks
Hope this post finds you well,
In order to provide the requested information, please create a new ticket using the technical support web.
Also, please inform us that on the new ticket you are about to create is linked to this one #00567652 .
Here is the technical support web:
https://support.nxp.com/s/
Best Regards,
Hector Villarruel
Support case #00568737