QCVS ACE

[jimccall]

I'm attempting to perform board check-out on a custom board. I have the processor in a good state (it has a valid RCW) and now I'm attempting to check out RAM using the QCVS and, afterwards, push the configuration into a TCL script to initialize the processor. When I try to run the QCVS DDR Validation tool's Validation Stage, it fails on "Write-Read-Compare Run 1" and gives the reason as: "Error configuring the target! - DDR initialization failed: D_INIT was not cleared by hardware!"

Write-Read-Compare Run 2 then fails with the reason "ERR_DETECT register not empty, test did not run."

When I look at my error capture registers, I see the following:

Err. capture registers:
0xE20, 0x00000000 0xE24, 0x00000000 0xE28, 0x00000000 0xE40, 0x00000080
0xE44, 0x00000000 0xE48, 0x00000000 0xE4C, 0x00000000 0xE50, 0x00000000
0xE54, 0x00000000 0xE58, 0x00010000  

It looks like there is an ACE being thrown. Is this a failure from the discrete RAM's side or from the T4240's side? Who actually does the automatic-calibration?

Is D_INIT not being cleared BECAUSE of the ACE or is the ACE being thrown because D_INIT is not cleared?

What would be causing these errors? 

I'm using discrete chips on each and every controller.

[yixuanhao]

Hello Jesse,

I was wondering if you were able to figure out the issue. I am seeing a similar issue with our board based on the T2080.

Best regards,

[xabiven]

Hello Jesse,

I am experiencing similar issue with aT2080based board I have developed.

Did you managed to solve your problem ? If yes, what was the root cause ?

Best regards,

[yixuanhao]

Hello Xabiven,

      I am face the same problem to you in a T2080 based board,i use QCVS DDRV to run it and all point response ACE ERR,have you slove it now?

Best regards,

[xabiven]

Hello yixuan,

I have solved my issue, but it was due to a PCB mistake: two control signal were inverted. So, the ACE error was justified because the DDR controller was unable to perform a correct initialization with this erroneous pinout.

If your hardware is correct (pinout, power supplies noise, clocks, calibration resistors, ....), the ACE error is most often due to timings errors.

From my own experience, the CW QCVS tool is efficient to compute operating ddr timing values.

Best regards,

[francescocaiazz]

Hi xabiven, I'm issuing a problem quite similar to yours, could you please tell me which signals were inverted?

[xabiven]

Hi Francesco,

This was a RAS and CAS inversion. It is not so easy to see because very similar to write, ... but so obvious when the error is located !

Best regards,

[yixuanhao]

Hi Xabiven,

      Thank u So much,i will check the hardware status again,mabye some wrong in hardware,becuase I have the same point with you that CW QCVS tool is efficient to compute operating ddr timing values,but I configurated arguments with DDR Datasheet recommendations ,run QCVS and compute operating ALL ddr timing values,without exception,All of them is wrong(tools shows ACE ERR).

  With my gratitude again for you.

[ufedor]

> Is this a failure from the discrete RAM's side or from the T4240's side?

There are two possible root causes of ACE bit set:
- Register setting is not optimized
- There is a HW issue

> Who actually does the automatic-calibration?

DDR controller

> Is D_INIT not being cleared BECAUSE of the ACE

Yes.

It is recommended to doublecheck:
a) DDR connection referring the AN3940 - Hardware and Layout Design Considerations for DDR3 SDRAM
b) DDR controller settings referring the AN4039 - PowerQUICC and QorIQ DDR3 settings
Validate the settings using the DDR Validation Tool:
http://www.nxp.com/assets/documents/data/en/user-guides/QCVS_DDR_User_Guide.pdf 
c) DDR powering and noise level amplitude at the AVDD_DDR
d) DDR MCK frequency

[ramkrishnan]

Hello Jesse,

I was wondering if you were able to figure out the issue. I am seeing a similar issue with our board based on the T1024. 

R,

Ram