PCIe1 issue on T4160RDB-64B

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PCIe1 issue on T4160RDB-64B

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vinothkumars
Senior Contributor IV

Dear  NXP friends,

I am working PCI interface on T4160RDB-64B machine.  I got no link for PCIe1 and I checked everything in RCW.

PLL1 only we used and PLL2 not used

Using SERDES1 Protocol: 27 (0x1b)
Using SERDES2 Protocol: 55 (0x37)
Using SERDES3 Protocol: 5 (0x5)
Using SERDES4 Protocol: 9 (0x9)

PCIe1: Root Complex, no link, regs @ 0xfe240000
PCIe1: Bus 00 - 00
PCIe2: disabled
PCIe3: disabled
PCIe4: Root Complex, x1 gen1, regs @ 0xfe270000
02:00.0 - 126f:0750 - Display controller
PCIe4: Bus 01 - 02

what could be the issue? need to done any configuration in u-boot side. 

Regards, VinothS

Regards,
Vinothkumar Sekar
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ufedor
NXP Employee
NXP Employee

1) Please provide as text attachment complete U-Boot booting log

2) Which EP device is used?

3) Into which RDB slot it is installed?

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vinothkumars
Senior Contributor IV

Hi Ufedor,

Thank you for your reply, and also I attached the log for your reference.

Regards, VinothS

Regards,
Vinothkumar Sekar
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ufedor
NXP Employee
NXP Employee

Why in the provided log:

Board: T4160RDB, Board rev: 0x00 CPLD ver: 0x0000, vBank: 0

What is this "T4160RDB"?

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vinothkumars
Senior Contributor IV

Hi Ufedor,

Our board is T4160RDB

CPLD is current bank and board revision is 0

Regards, VinothS

Regards,
Vinothkumar Sekar
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ufedor
NXP Employee
NXP Employee

Fine.

Then you have to provide additional information:

1) complete processor connection schematics as searchable PDF

2) measured frequencies of all SerDes reference clocks

3) Which EP device is used?

4) How the EP device is connected?

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vinothkumars
Senior Contributor IV

Hi,

Please find the attachment for Processor connection schematic.

Regards,

VinothS

Regards,
Vinothkumar Sekar
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ufedor
NXP Employee
NXP Employee

2) measured frequencies of all SerDes reference clocks

3) Which EP device is used?

4) How the EP device is connected?

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vinothkumars
Senior Contributor IV

Hi Ufedor,

Serdes1 Frequency -  100MHz

Serdes2 Frequency - 156.25MHz

Serdes3 Frequency - 100MHz

Serdes4 Frequency - 100MHZ

EP device is PCI switch

Regards, VinothS

Regards,
Vinothkumar Sekar
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ufedor
NXP Employee
NXP Employee

Required additional information:

1) complete processor connection schematics as searchable PDF to check PCIe connection and SerDes powering

5) read the PEX control/status register 0 (CSR0) several times and provide values

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