Missing D1_MCK output

[gregbuchannan]

I am bringing up a new T2080 board, and have no DDR D1_MCK0 output.  I am using CodeWarrior for debug, and using the same RCW settings I see D1_MCK0 output on the T2080 RDB board.  I've checked all voltages.  D1_DDRCLK looks good.   I see D1_MCKE0 toggling.  Any ideas?

Thanks.

[ufedor]

Is the processor capable to successfully complete the POR sequence? - refer to the T2080 RM, Figure 4-1. Power-on reset sequence.

What are levels of the RESET_REQ_B and ASLEEP?

Have you performed the DDR controller initialization? Which script is used?

[gregbuchannan]

RESET_REQ_B and all associate reset inputs are not being asserted.  ASLEEP is high after POR, but is deasserted when I enter the DDR tuning routine.  The DDR controller is being initialized by third-party tuning SW running over CodeWarrior JTAG pod.  Unfortunately I don't have visibility into the initialization routine, but when I connect to the T2080 RDB with the same SW and same RCW, I get a good D1_MCK output.

[ufedor]

Please doublecheck the design and ensure that all notes after the 'Table 1. Pinout list by bus' in the 'QorIQ T2080 Data Sheet' are fulfilled. Pay special attention to the note 5.