Inquiry regarding T2080 Boot Flash settings

[ryudaejin]

Dear friends,

I'm using T2080 + VxWorks bootloader + NOR boot flash (tACC=120ns, tOE=35ns).
When powering on, it intermittently boots only up to bootlaoder (unable to load vxworks kernel).

I am using a TRAD_NOR of 97ns for the T2080 CPU's IFC_FTIM1. I think it fully satisfies the NOR flash's tOE(35ns).
1. Do I need to modify TRAD_NOR to satify the tACC(120ns)?
2. When accessing NOR boot (tACC=120ns, tOE=35ns) from the T2080(ifc_clk=11.5ns), could you please tell me the frequently configured IFC_FTIM0~3 values and known precautions?

Thank you in advance for your answer.

[June_Lu]

@ryudaejin Any update?

[ryudaejin]

Dear June-Lu,

I am still curious why set TRAD to 130ns (greater than tACC) in the u-boot code, but your answer was very helpful.

Thank you for your help.

[June_Lu]

Please confirm the definitions of TACC and TOE.

I checked the S29GL01GT datasheet I have. According to it, TACC is the address-to-output delay, tCE is the chip enable–to-output delay, and tOE is the output enable–to-output delay. Are these definitions the same as in your datasheet?

Regarding Figure 17, is it the same as the one shown below?

[ryudaejin]

Dear June-Lu,

I checked my datasheet again, and it is the same.

[June_Lu]

The T2080 RM formula for TRAD_NOR explicitly uses TOEmax plus 2*Board Delay plus setup time. It's related to the tOE. tACC/tCE should be checked against the combined path tACO + tRAD, not against TRAD_NOR alone.

The parameters in the T102xRDB.h will leave enough margins to access the board. You could using all the setting to check if it could solve your issue, if it could solve your problem, then you could adjust your parameters per the RM and datasheet.

Any further question, please kindly share the waveform and all IFC registers setting.

[June_Lu]

Would you kindly confirm your IFC module input clock? 

According to the T2080 Reference Manual (Figure 4-3), it is ip_clk, which is 1/2 of the platform clock.

The valid range of the platform clock is listed in the datasheet (Table 121), and it depends on your configuration.

Could you please check whether IFC_CLK is the same as ip_clk?

I checked the T1023RDB platform using the S29GL01GS (although it is NO-ADM). It is very similar to S29GL01GT, and its timing configuration can be used as an initial reference. 

On this platform, the platform clock is configured to 400 MHz: 

https://github.com/nxp-qoriq/u-boot/blob/LSDK-1703/include/configs/T102xRDB.h#L328

Regarding additional delays (for example, those affected by temperature), you may refer to the QorIQ T2080 Datasheet, Figures 20 and 21, which show a maximum output delay of 2.5 ns and a minimum output hold time of –2 ns.

When tACO and tRAd are configured, the actual CE_B and OE_B timing will be longer than the programmed values by at least 0.5 ns. Even considering variations due to temperature and layout, 3 × 11.5 ns = 34.5 ns compared with the 23 ns requirement still provides sufficient margin.

You may also refer to the T2080 Reference Manual, Section 13.4.2 (Programming Model for Flash Interface Timing), which allows adding one more IFC module input clock cycle to further enlarge the margin.

In any case, it is recommended to verify the waveform using an oscilloscope to confirm that the timing meets the requirements.

You could set the waveform and IFC registers setting to further checking.

[ryudaejin]

Thanks June-Lu,

I'm using clock as below.

 - Platform clock: 533.33Mhz

 - ip_clk :  266.66Mhz (IFC module input clock)

 - IFC_CLK : 88.88Mhz (IFC external clock)

Looking at the reference data you provided (T102xRDB.h), TRAD is set to 0x1A. It's platform clock is 400Mhz, then ip_clk is 200Mhz, so I extimate that TRAD = 5ns * 26(0x1A) = 130ns.

In other words, it appears that TRAD is designed to satisfy the Flash's tACC(120ns) rather than tOE(35ns)

[June_Lu]

Sorry my OoO.

By comparing Figure 17 in the S29GL01GT datasheet with Figure 13-33 (Read Cycle Timing) in the T2080 Reference Manual, the following timing relationships should be satisfied:

- tACO + tRAD shall be no less than tACC.

- At the same time, tRAD shall be no less than tOE.

1. TRAD_NOR = 97 ns satisfies the tOE requirement (35 ns). However, the tACO requirement also needs to be checked. According to the 120ns requirement, tACO should be greater than 23 ns. If ifc_clk = 11.5 ns, this implies that tACO should be configured to no less than 3 clock cycles.

2. The IFC_FTIM0 parameter is related to the address latch timing. Confirm whether the address lines work reiable before chip enble. It is recommended to use an oscilloscope to observe the read access sequence on the bus signals to further verify whether the timing meets the requirements.

Thanks

[ryudaejin]

Thanks June-Lu

TACO is using 11 cycles and I have confirmed that the address prior to the CS has stabilized. 

It appears to satisfy the requirements listed in the datasheet, but intermittemnt boot errors are still occurring.

When I inquire withAO tools like ChatGPT, they suggest that TRAD must satisfy tACC+delay(affected by temperature, etc.). What are your thoughts on this?

And, Could you tell me the T2080 boot loader settings commonly used, such as u-boot?

(IFC_FTIM0/1 settings and boot flash model)

Thank you.

[June_Lu]

Please kindly share the NOR Flash timing sequence diagram for tOE and tACC, or the corresponding NOR datasheet.

If possible, please also indicate the page numbers where these parameters are specified.

Thank you.

[ryudaejin]

Thank you for your reply.

I'm using S29GL01GT from cypress.

tACC=120ns (max) and tOE=35ns(max), tCE=120ns(max).