Have a great day, my name Sergey
CSn (chip select n) selected if,
{BASE_ADDRn[0:7], (BASE_ADDRn[8:23] & AMn[0:15])} == {SYSTEM_ADDR[39:32], (SYSTEM_ADDR[31:16] & AMn[0:15])},
where
* SYSTEM_ADDR is a 40-bit incoming address from the system side. Index 39-32 represents 8 address msbs
* SYSTEM_ADDR[31:16] represent the next lower 16 address bits and the remain 16 lsbs are not used in the bank selection
* BASE_ADDRn[0:8] and BASE_ADDRn[8:23] is defined in the IFC_CSPRn_EXT and IFC_CSPRn.
* The address mask AMn[0:15] is defined in the IFC_AMASKn
1) HOWEVER after reset, until a first write transaction occurs to update AMASK0 register, all the transactions coming from the system side will always be mapped to CS0. After receiving the first write transaction to update AMASK0, the chip select decoding logic will work as per the above mentioned equation. Ensure that AMASK0 has been set after reset.
2) If you are sure that AMASK0 has been set then ensure that above mentioned equation does not provide overlapped regions for CS0 and CS1.
3) If the CS0 and CS1 region settings are not overlapped then ensure that software really uses address for CS1 region in your test.
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