Sorry for delayed response to this.
Time base is always enabled, and there is no way to disable it via HID0 register, the only way to disable Time Base is to externally assert tben signal by SoC hardware (memory-mapped register). The explanation why it is implemented in this way - is given in E5500 Core Reference Manual, Section 2.8:
The only enable/disable control over the time base is the TBEN core signal, controlled by the SoC through a memory-mapped register, allowing control of stopping and starting the time base on any core.
MAS7 register updates are alway enabled. The explanation, why it may be useful to disable it - is given in BookE, description of HID0[EN_MAS7_UPDATE] field:
Implementations that support this bit do not update MAS7 (upper bits of RPN (RPNU) field) when hardware writes MAS registers via a tlbre, tlbsx, or an interrupt unless this bit is set. This provides a compatibility path for processors that originally offered only 32 bits of physical addressing but have since extended past 32 bits.
As there is no e5500-based processors, that originally offered only 32 bits, maintaining this compatibility is not necessary.