DDR4 configuration fail - ACE Error

[ivan_pfarher]

I am trying to configure DDR4 (MT40A256M16 - 5 discrete devices, one is for ECC) with T1022 processor using Lauterbach probe and the registers configuration generated by Codewarrior-QCVS

Codewarrior Version: 10.5.1.

QCVS Version 4.5.0

How I do that:

1. Configure DDR4 on Codewarrior-QCVS.
2. Generate code.
3. Translate .tcl script generated by Codewarrior-QCVS to Lautebach PRACTICE script.
4. Run Lauterbach script which detect the processor, configure the RCW, configure the UART and print to the console and configure the DDR4 Controller.
5. I check that all registers are configured on the processor.

Once the registers are set in the DDR4 Controller and bit MEM_EN is set, DDR Error ACE turns on as you can see in the screenshot (TRACE_32-regs.jpg) attached. I know that the ACE bit means an error in the training process.

Also you can see some of the debug registers in the screenshot.

Q1: I would like to know why it is failing  and if the DEBUG registers can give us more information. Could you provide that information?

In addition you can find attached the RCW (PBL.pbl) and the DDR register configuration (ddrCtrl_1.tcl).

I also tried without success:

• Reduce the clk freq from 800MHz to 650MHz
• Measurement of 1V2 and 0V6 voltage are OK.
• Check termination of MDICx signals are OK.
• Check clk presence OK.

Q2: Is there any example code to configure DDR4 available? It could be C code, I have uboot running, but failing when it reach the DDR configuration because is trying to read SPD.

Any help will be really appreciated.

Thank you.

[ufedor]

1) You wrote:

> Configure DDR4 on Codewarrior-QCVS

Which exactly parameters you have specified for the QCVS DDR Tool to obtain the registers settings?

Please provide screenshot of the filled DDR configuration pane (see attached).

2) Please provide the processor connection schematics as searchable PDF for inspection and Excel table containing PCB traces lengths for all signals of the DDR interface.

[ivan_pfarher]

Hi 

Please find attached the QCVS configuration screenshots.

Note that the initial configuration was for 1600MT/s and ECC enable, after it didn't work, those parameters were modified from QCVS.

Regarding the track distances you can find the info in the spreadsheet attached.

I need to ask for schematics approval in order to post them here, it will come later.

[ufedor]

Concerning provided Excel table - it does not contain the requested data.

Please provide a table containing lengths of ALL PCB traces lengths of the DDR interface signals - i.e. address/control/data.

[ivan_pfarher]

Hi ufedor,

Attached you can find the PCB length updated.

For Addr/ctrl i have provided the length of the signal to the first chip (U6). If you also need the lengths between the chips it gets a bit tricky, but it is about 11-12mm for all the lines varying with layer.

Your assistance is really appreciated.

Thanks

[ufedor]

You wrote:

> If you also need the lengths between the chips it gets a bit tricky

Excuse me, how in this case you filled numbers into the DDR Configuration "DDR4+config+real+tracks.jpg"?

What are MCK segments lengths?