Cache Scratch Page?

[stevenstarnes]

I am currently trying to inject L2 Cache errors into a e6500 core and in section 4.11.5.3 of the EREF manual it states to use a scratch page for injecting errors. I assume this is so none of my program data gets corrupted? I have tried searching for information on how to set up a scratch page but I can't find anything?

[alexander_yakov]

"Scratch page"  is just a page, filled by some test data and not containing any valid data, this page is used only for L2 cache error injection testing, so no user data is corrupted during these tests.

Have a great day,
Alexander
TIC

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[stevenstarnes]

So how would I do this? Would I setup a small section of RAM in my TLB to be cache enabled? Right now I have 2GB TLB page for RAM that is cache inhibited.

[alexander_yakov]

Yes, to test cache error injection you should have some part of memory cache-enabled in TLB attributes. All other memory should be cache inhibited, this is correct.