CPLD in RFDB T1042

[faizmajeed]

Hi!

I am using T1042 and designing a board using reference board of T1042. I am using 4 flashes and they are directly connected to IFC in my board and IFC is sending control signal to CS,WE and all other signals. But in reference design board, CPLD is controlling all the control pins of Flashes. Please tell me if it is necessary to add CPLD in my board and control my flashes through CPLD

Thank You

[ufedor]

There is no strict requirement to use CPLD for the IFC interface - it is up to the board designer.

[faizmajeed]

As i am getting help from reference schematic.

1) I cannot understand the purpose of XOR gate with MSB of Flash addresses and CPLD output.

2) Also CPLD getting IFC DATA but not IFC's adress accept few pins.

Please explain my these two questions

Thank You

 

[ufedor]

1) This is to implement "virtual banks" in the NOR Flash.

For example the CFG_VBANK0 physically swaps halves of the Flash, so it is possible to have two bootable images - main and reserved.

2) I believe that your question is connected with implementation of internal CPLD registers.

[faizmajeed]

1) Is it necessary to keep two bootable images?

2) Yes, can you please explain some logic that what CPLD is doing with IFC data.

[ufedor]

1) It is up to the board designer.

2) Internal registers are used to control the CPLD operation in accordance with the RDB documentation.

[faizmajeed]

ok. i am on the final stage of my board designing. just inform me that what controls can i give to CPLD relating to flashes that IFC can not perform. If no need for CPLD to interface NOR with IFC then please inform me so that i can finalize my design.

Thank you

[ufedor]

Excuse me, please refer to my first response.