MPL115A1 DOUT not work

[dhavalpatel]

I have connected MPL115A1 as per data sheet and not using shutdown option so it is connected VDD.

I am trying to read coefficient and ADC data via SPI bus.

I am sending following packets:

start conversion  and wait for 3ms.

Read Pressure ADC (MSB and LSB)

Read Temp ADC (MSB and LSB)

Read A0 (MSB and LSB)

Read B1 (MSB and LSB)

Read B2 (MSB and LSB)

Read C12 (MSB and LSB)

I have attached screen shot of SCLK, CS, DOUT and DIN lines

Surprisingly I can't see any data on DOUT.

Also, I have tried to disconnect DOUT from rest of ckt and probed on  MPL115A1 Pin 6. Though I can't see any data coming out. I have tried another IC incase first one is not working!! No improvement.

Any help?

[dhavalpatel]

Just wonder whether I got correct ICs from supplier or not?

It has marking M1PR COC (or M1PR C0C).

[TomasVaverka]

Hi Dhaval,

Yes, M1PR is the correct marking for the MPL115A1 (SPI version), M2PR is for the MPL115A2 (I²C version). The next 3 signs denote the production series.

The timing seems to be correct now. If you ordered more MPL115A1 parts, have you tried using another device? Could you please post here your schematic to make sure the problem is not there?

Regards,

Tomas

[dhavalpatel]

Hi Tomas,

I have tried this as well. No luck.

Not adding all Screen shots.

[TomasVaverka]

Hi Dhaval,

I assume the problem is in the base value of the clock (SCLK). The MPL115A1 uses the ‘Mode 0′ SPI protocol, which means that an inactive state of clock signal should be low and not high. If you use a hardware SPI, it corresponds to CPOL = 0 setting.

I hope it helps. If not, please let me know and I will continue in investigating this issue.

Regards,

Tomas

PS: If my answer helps to solve your question, please mark it as "Correct". Thank you.

[dhavalpatel]

Hi Tomas,

Thanks for reply. I have tried mode 0 but no luck. (not adding all screen shot here)

[TomasVaverka]

Hi Dhaval,

Looking at your screenshots, the clock signal is now correct, but the data are captured on the falling edge which is incorrect. Make sure that the data are captured on the leading edge of clock signal and changed on the falling edge (Mode 0 – CPOL = 0 and CPHA = 0).

I hope this helps.

Regards,

Tomas