MMA8451Q in sleep mode does not generate events?

[tricon]

Dear Community!

During development another question arose concerning the system events.

What's our plan

We want the accelerometer to run in sleep mode until a transient interrupt occurs. When a transient happens the accelerometer wakes up and switches to a higher data rate. Also it generates a transition on INT1. Now the µC reads the FIFO of the MMA. This works very fine.

Moreover, we want to trigger single pulse events while the MMA works at the sleep ODR. A slow ODR is fine for this application. Since we want to conserve as much power as possible the accelerometer should stay at it's sleep ODR. A transition on INT1 is just fine for us to indicate the µC a pulse IR happened.

Where's the catch

Everything works fine except the pulse interrupt. It is never generated when the accelerometer's asleep. Only when a transient event occurs which wakes the MMA a pulse interrupt is triggered.

For testing I forbid the accelerometer to go to sleep and stay awake using a ODR of 50Hz (which is normally used at sleep mode). In this case pulse interrupts were generated correctly (pin INT1 showed a transition). Therefore it seems to me that interrupts are only generated when the accelerometer is not asleep. However, the datasheet of the MMA8451Q states at page 41 that “All enabled functions will still function in SLEEP mode at the SLEEP ODR”. So what do I get wrong?! Is the pulse event deactivated at sleep mode or not?

For the sake of completeness the accelerometer’s configuration:

• ODR when active: 400Hz, low power (at 0x2A and 0x2B)
• ODR when asleep: 50Hz, low power (at 0x2A and 0x2B)
• Transient interrupt activated at a certain threshold (at 0x1D, 0x1F and 0x20)
• Pulse interrupt activated with a very low threshold (at 0x21 to 0x27)
• Only the transient interrupt change the accelerometer from sleep to active (at 0x2C)
• Interrupts of Pulse, Transient and Sleep<->Wake are routed to pin Int1 (0x2D and 0x2E)
• Moreover, the FIFO is continuously running in circular mode

Thanks for your help!

Best regards,

Johannes

[TomasVaverka]

Dear Johannes,

I have tried to reproduce your settings and found that the tap detection block functions in sleep mode since the PULSE_SRC register is being updated, but the pulse interrupt indeed is not being generated.

It seems that in sleep mode, when the WAKE_PULSE bit = 0, the pulse interrupt is "deactivated" although INT_EN_PULSE = 1. I have requested assistance from the design team to verify the implementation on the ASIC. I should have a final answer by tomorrow.

Regards,

Tomas

[tricon]

Hey Tomas,

any updates on this topic yet?

[TomasVaverka]

Hi Johannes,

I do apologize for the delayed response, unfortunately I have not heard back from the design team yet. I will definitely update this thread a soon as I have an answer.

Regards,

Tomas

[tricon]

Hi Tomas,

three weeks passed by since your last update. Do you have any news on this topic yet?

Best regards,

Johannes

[TomasVaverka]

Hi Johannes,

I do apologize for this late reply, it was difficult to get an answer from the design team during a period of vacation.

However they confirmed, that the pulse interrupt is not generated in sleep mode if the WAKE_PULSE bit = 0. The functions in sleep mode are only used to wake up the device if the corresponding WAKE_x bit in the CTRL_REG3 is set.

Regards,

Tomas

[tricon]

Hi Tomas,

thanks for your very fast reply! I am courios what your ASIC team reports! :smileycool:

Best regards,

Johannes