MMA8451 Interrupts and Reset Behavior?

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MMA8451 Interrupts and Reset Behavior?

Contributor I

I have some questions about the MMA8451 interrupt architecture and software reset (RST bit) behavior:

(1) Is the RST bit self-clearing?  The datasheet mentions a boot process - is this just the initial power on boot?  

(2) What is the timing regarding RST?  Specifically - is there a coming-out-of reset delay?  Can the part be used immediately after coming out of reset (i.e. streamed I2C communication that takes it out of reset won't miss the next byte)

Regarding interrupts - does going into standby (SYSMOD = 0) clear an active interrupt?  

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NXP TechSupport
NXP TechSupport

Hi Ian,

1 Yes. When the RST bit is set, the boot mechanism resets all functional block registers and loads the respective internal registers with their default values. At the end of this boot process, the RST bit is internally hardware cleared.

2. We recommend a 1 ms delay between issuing a software reset and attempting communication with the device over the I2C bus.


Regarding interrupts, going into standby mode does not clear active interrupts.

Best regards,


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