Can the CPU be put in Slow Clock mode while an accelerometer frame is being constructed (FXLC95000CL)

[nickjensen]

I ask that question in hopes of doing the prior frame's filtering & analysis computation while a subsequent frame is being built.  If the computation is shorter than the 207uS frame construction, I'm hoping to save more power by going into slow clock mode as soon as possible.

I am surprised that I can't find any FXLC95000CL discussions.  Is the part so new that no one is using it??

Or is it so easy to use that no one has questions?

Nick

PS. In the process of evaluating using this part.  Any comments about using it would be appreciated.

[JackITB]

Hi Nick,

Are you using the ISF framework and associated example, e.g. GetAccelData project ?

Your proposed scheme is doable but I'm gonna check if it can be handled by the ISF framework.

Regards,     Jacques.

[nickjensen]

Hello Jacques!

Currently I'm doing back of the envelope projections before deciding to proceed with getting the development board.  Trying to decide between the FXCL9500Cl & the MMA9559L.  But very low power is a primary objective of my application.  So the idea of putting the App onboard this sensor is very appealing.  The app doesn't have to do much more than a coordinate rotation of the accelerometer matrix followed by an IIR filter followed by some simple accumulation.  Given the single cycle multiplier and barrell shifter, it appears that my calculations could be completed in less than the 207uS minimum time for a frame calculation.  IF SO, and if I could switch to the slow clock mode even earlier, running this code within the sensor should save significant power.

I just found ISF1P195K_SW_REFERENCE_RM.pdf that was referenced in the slides from the Texas training which looks to be a key document that I missed.  Still sifting though it...

Are their other important documents that might shed info about this sort of thing?

Nick