S32K396 BIST

[nxf47333]

Hi Team,

My customer Changan used K396 and de-couple CM7_0&CM7_1 as two application core, CM7_2 as master safety core, from the SAF BIST_UM. here say, recommended to run BIST from CM7_0 and other core should be disabled.

but customer used CM7_0 as main core, and booted CM7_1 and CM7_2 with MC_ME, whether it is OK to run BIST in CM7_2 with CM7_0&CM7_1 active but stuck some where.

[nxf55526]

Hi Alvin,

The first core to boot is HSE core and then it is software choice whether to bring up Core0/1 or Core 2(/3). There is no hardware gating that is preventing bringing up of Core0/1 ahead of Core 2(/3) by HSE core. However, as per safety concept, Core 2(/3) is the master safety core which should boot before the other cores to ensure safe boot. 

So, flow should be : 

1. HSE core brings Core 2(/3) out of reset after secure boot.

2. Core 2(/3) runs BIST while Core 0 and Core 1 are in reset.

2. After BIST is complete, chip goes through functional reset and then Core 2(/3) un-gates the clock of Core 0 and Core 1 via MC_ME. 

Kind Regards,

Avni