Hi Team,
Could You please Answer the below queries Related to Safety.
1. Allocate decomposed ASIL-B software requirements on both the realtime cores (M7) and the performance cores (A53) (eg. ASIL-B(B) on M7 running AUTOSAR and QM(B) on A53 running AAOS-BI)
- is that possible?
- if possible do we have any reference documents to attach to my safety Case?
2. Reset all the performance cores (the A53 cores) independently from the realtime cores (M7 cores) in case of errors affecting performance cores
- is that possible?
- if possible do we have any reference documents to attach to my safety Case?
3. I would plan to run safety SW on the performance cores configured in ASIL-B mode (non lockstep cluster mode)
According to the S32G safety manual (FMEDA), reaching the ASIL-B on performance cores in non-lockstep/decoupled mode requires reciprocal SW comparison (SWCMP)
- what does that mean in practice?
- how can we practically implement it on a platform (ie. In a generic way, without prior knowledge of the safety load)?
