S32G3 CMU_FC tolerance of clock

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S32G3 CMU_FC tolerance of clock

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zeyu_yan
Contributor III

Hi,

    when I configure sboot in SAF for S32G3,I can not find any spec of the tolerance of the monitored clock.

    what is the CMU_FC minimal/max frequency for each monitored clock?

zeyu_yan_2-1665997273290.png

zeyu_yan_3-1665997332101.png

 

 

zeyu_yan_0-1665996980574.png

zeyu_yan_1-1665997052999.png

 

 

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Yashwant_Singh
NXP Employee
NXP Employee

Hi

Usually, the variation of clock frequency is captured in the datasheet of the device. We request you to look into the datasheet of the device to find the information you are looking. In case you are unable to find the relevant information in datasheet, you can post a query in product specific forums since this is not really safety specific topic. 

The link to S32G product forum is here:

S32G - NXP Community

Regards

-Aarul Jain and Yashwant Singh

 

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nxf65498
NXP Employee
NXP Employee

Hi, 

The section 69.5.2 Programming HFREF and LFREF, describe the monitored clock variation, formula to calculate min/max frequency for monitored clock (as shown below) . Please refer S32G3 RM , Rev. 2, 09/22. 

nxf65498_0-1666254771718.png

  • Any spec of the tolerance of the monitored clock.

-> CMU_FC has an expected maximum deviation of ± 3 monitored_clock cycles (CMU_FCVAR+ = 3, CMU_FCVAR- = –3). Determine the specified variation of the monitored_clock (1.1%).

  • what is the CMU_FC minimal/max frequency for each monitored clock?

-> The Min/Max frequency of monitored clock depends on which clock is selected as monitored clock again reference clock. The "section 24.8.2 Clock input source" describes the reference and monitor clock for each CMU. The "section 24.2 clock sources" provides the frequency info for different clock.  

I hope it helps. Please let us know anything isn't clear.

Best regards,

Bhavik

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zeyu_yan
Contributor III

Thank you for your reply.

 

I can find the monitored clock for each CMU instance in 24.8.2 table clock input source

for example DDR_CLK,the instance is CMU_FC_20,

zeyu_yan_0-1666334995215.png

zeyu_yan_1-1666335038604.png

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but I can not find the max/min clock limit for DDR_CLK when S32G3 is connected to a LPDDR.

In other word, is it  ok if

     1)the PLL of DDR_PLL is locked

     2)the output of DDR_PLL(DDR_CLK) is 50% of the rate output of the DDR_PLL?

 

 

 

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zeyu_yan
Contributor III

I think the main problem is how to specify the variation of the monitored_clock

zeyu_yan_0-1666339762909.png

 

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Yashwant_Singh
NXP Employee
NXP Employee

Hi

Usually, the variation of clock frequency is captured in the datasheet of the device. We request you to look into the datasheet of the device to find the information you are looking. In case you are unable to find the relevant information in datasheet, you can post a query in product specific forums since this is not really safety specific topic. 

The link to S32G product forum is here:

S32G - NXP Community

Regards

-Aarul Jain and Yashwant Singh

 

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zeyu_yan
Contributor III

Thank you 

I understand what you mean.

The spec in datasheet below is the clock frequency range,I am not sure is it proper to   choose the value in the table below as the tolerence of the clock.

 

zeyu_yan_0-1667273700798.png

zeyu_yan_1-1667273710923.png

 

 

 

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