How does SPLL monitor work

[sfjia]

Hi 

We are working on functional safety application of S32K144 and have a query on SPLL monitoring.

According to safety manual,  there is a loss of lock monitor to SPLL, does it compare the frequency of SIRC and SPLL? If yes, why is there only one line in the clock diagram？

[sfjia]

Hi, 

Can we change the upper and lower range value of SOSC and SPLL monitor funtion? 

How to achive a power-on test to the clock monitor function considering it could be a latent fault?

Thanks!

[aarul]

Hi

1. No the range cannot be changed.

2. We do not have a power-on test for clock monitor and so we do not claim any coverage over it in Safety Analysis. Just to add, multiple point failures of clock and monitor are also covered by other safety mechanisms like WDOG and so we do not think this is a risk for an ASIL-B application.

Regards

-Aarul

[nxf55526]

Hi sfjia,

Yes that is right. There is a loss of lock (LOL) monitor to SPLL. The LOL monitor is a digital counter based implementation with respect to SIRC clock.

The clock diagram represents the LOL monitor without showing its reference SIRC clock. The dotted line in below diagram shows the SIRC reference for the SPLL LOL monitor.

Hope this answers. 

Kind Regards,

Avni