Dear NXP Experts, We have some detailed questions about the FMEDA from NXP, could you please help to clarify them? Thanks! Q1: We use several S32KXX series MCUs in our products. There are several FMEDA excels (classified as Clock, Core, Flash, Peripheral, Power, SRAM etc.) which we can customize with the support from local FAEs. Inside the excel for "Peripheral" element, I can find a "Pin example" failure rate. Does it mean that Pin example x Pin number = package failure rate by IEC TR62380? (I can find the package failure rate inside a separate document based on calculation using IEC TR 62380, but there is no clear hint how package failure rate is used in FMEDA excels) Q2: Just take one example, for S32K116 I can find a document titled "S32K116_FIT_Rate_Calculation.pdf", performed according to IEC 62380, where Die failure rate is quite low (0.233). However inside the FMEDA excels, the total failure rate for a SRAM is much larger (~300 fits) than that inside the above document. As I understand, the failure rates for Soft error upsets for RAM / Soft error latch-up for RAM / Soft error rate of flip-flops should come from JESD89. Is there any further evidence about how this part of failure rates is calculated and then used in final FMEDA excel sheet? Thanks BR Francis
