Parallel GPIO Register Write to Pin Latency

[Gene1000]

What is the maximum latency between an R52 core write to a SIUL2 parallel GPIO output register (e.g., SIL2_0.PGPDO1) and the GPIO pins starting their transitions?

I understand that pin settings for RDSON and external loading will effect final rise/fall times, I'm just looking to understand latency internal to MCU.  I assume this latency would be identical for 3.3V, 1.8V/3.3V, and 1.8V pins.

[alejandro_e]

Hello @Gene1000 

I am glad you found the information useful. If you have any new questions in the future do not hesitate in creating another post. And thank you for selecting my last reply as an accepted solution.

Best regards

[Gene1000]

Hi @alejandro_e ,

We will need the capabilities of the 594BGA package.

Sorry for the miscommunication, I see why you would make the assumption I had a test setup.  I'll try to put that out up front next time when I have more of a can't find anything about it in the datasheet type question.

Unfortunately unlike some of the NXP evaluation boards like the MIMXRT1170-EVK that I have worked with (less than $200 with onboard debug probe...amazing!), we wanted to do more paper research before diving into the more costly S32z hardware.

Thanks for your help and I look forward to your results next week.

Note: Not sure if it will matter but I'm interested in using the parallel GPIO registers (as opposed to single pin registers) to read/set multiple pins at once.  So if you use that in your tests that would be great.