Inquiry on Data Value Trace Support for S32Z27 ETM-R52

[Luke_K]

Hello,

We are currently setting up a real-time debugging environment using the S32Z27 processor and require clarification on its trace capabilities.

1. Does the ETM-R52 implementation in the S32Z27 support Data Value Trace in addition to Instruction Trace?

2. If supported, could you please point us to the specific section in the Reference Manual or provide technical notes that describe the register configurations (e.g., TRCCONFIGR.DV) required to enable data value tracing?

3. If this feature is not implemented, could you please provide the technical confirmation, such as the fixed value of the ID register (e.g., TRCIDR0.DATSIZE), for this specific device?

4. Could you provide a specific method to determine the hardware implementation status by reading ID registers, such as TRCIDR0, using TRACE32 commands or register windows (e.g., PER window or Data.List)?

5. If I encounter a "Feature not supported" error when executing the ETM.DataTrace AddressValue command, can this be considered definitive proof of a hardware limitation of the S32Z27? Is there any other diagnostic procedure to confirm this?

We look forward to your detailed technical guidance.

Best regards,

[Bio_TICFSL]

Hello,

The Arm Cortex-R52 implementation in the NXP S32Z27 typically does not support Data Value Trace. While the Cortex-R52 architecture itself allows for optional data trace, most automotive-grade implementations (including the S32Z series) focus on Instruction Trace and Data Address Trace to manage the extremely high bandwidth requirements of real-time cores. 

In the S32Z27, the Embedded Trace Macrocell (ETM) is generally limited to:

• Instruction Trace: Tracking the program flow.
• Data Address Trace: Tracking the memory locations accessed (if configured), but not the actual data values being read or written. 

Identification via ID Registers

To definitively confirm the hardware capabilities of your specific silicon, you can read the ETM ID registers through your debugger.

Key Register: TRCIDR0 

The TRCIDR0 (ID Register 0) contains bitfields that describe the supported data trace features.

• Bit [27:24] (DATSIZE): This field indicates the data value trace size. If this field is 0x0, data value tracing is not implemented.
• Bit [16] (TRCBB): Indicates if branch broadcast is supported.
• Bit [12] (COND): Indicates if conditional instruction tracing is supported. 

TRACE32 Diagnostic Method

You can use the following methods in Lauterbach TRACE32 to inspect these values:

1. Register Window: Use the command PER.view /CoreSight and navigate to the ETM-R52 component to see a decoded view of the ID registers.
2. Data Dump: Execute Data.dump E:<ETM_Base_Address>+0x1E0 (0x1E0 is the offset for TRCIDR0) to see the raw value.
3. Command Line:
   t32

   PRINT "ETM IDR0: " ETM.CONFIG(0) ; or appropriate register access command

   Diagnostic Errors and Confirmation

   If you encounter the error "Feature not supported" when executing ETM.DataTrace AddressValue, it is almost certainly a hardware limitation of the S32Z27's ETM implementation. 

   • Definitive Proof: If TRCIDR0.DATSIZE is 0, the hardware logic for capturing and packetizing data values is physically absent from the silicon. No software or debugger configuration can enable it.
   • Alternative Diagnostics: Check the TRACE32 system settings using ETM.REPository. This window often lists all detected ETM features. If "Data Value" is grayed out or marked as "None/0-bit," the feature is not present. 

   Summary Table for S32Z27 ETM-R52

   Feature	Typical Status in S32Z27	Register Check
   Instruction Trace	Supported	TRCIDR0.PROGFLOW == 1
   Data Address Trace	Often Supported	TRCCONFIGR.DA
   Data Value Trace	Not Supported	TRCIDR0.DATSIZE == 0

   Note: For high-speed data monitoring without ETM Data Trace, consider using the Instrumentation Trace Macrocell (ITM) for software-driven instrumentation or the LPDDR4 interface to export large trace buffers to external memory if supported by your specific board.

   Regards