Implementation of the system counter

[danieljcoliveira]

Hi all,

According to Arm's AArch32 Architecture Reference Manual, the Generic Timer includes a memory-mapped system component that provides the system counter — the part that actually measures the passage of time in real time (Ref: The Generic Timer in AArch32 state, G6-11749). This system counter exposes registers like CNTCR, CNTCV, CNTFID0, etc.

However, this seems to be implementation-defined, because in the Cortex®-R52 Technical Reference Manual, it's explicitly stated that:

"The Cortex-R52 processor does not include the system counter (...); it resides in the SoC."

Given that, my question is: 

Are the S32Z System Timer Module's (STM) typically used as the implementation of the system counter that feeds the Generic Timer registers accessed via coprocessor space (coproc == 0b1111)?

If yes, then:

• Does that mean the only interface to this system counter is through memory-mapped registers (e.g., starting at 0x76200000)?

• And therefore, the architectural registers like CNTCR, CNTCV, etc., do not exist or are not accessible in a standard way on Cortex-R52 systems?

Thanks in advance!

[Joey_z]

HI,danieljcoliveira

Thank you for your information.

Refer to the Arm® Cortex®-R52 Processor Technical Reference Manual, about the R52, The Cortex-R52 processor does not include the system counter. This resides in the SoC. a set of Generic Timer registers are allocated to the (coproc==0b1111) space.

S32Z have the RTU.GPR to configure the Cortex-R52 processor.

Also, The CNTDV function is System Counter Divider for Cortex-R52 processor Generic Timer.

The STM is System Timer Module， Each RTU subsystem has four STM instances it is different with the system counter。

BR

Joey

[raz3l]

Thank you for the brief clarification. So, if I understood correctly:
- Cortex-R52 doesn’t have its own system counter.
- There is still a set of Generic Timer registers at coproc 0b1111
- RTU.GPR allows configuration of the R52 processor

My follow-up questions would be:
- Where exactly is the system counter implemented in the S32Z? (any block name, base address)
- Is there any SoC-specific way to directly read the system counter value (e.g., a memory-mapped alias) ?

[Joey_z]

hi,raz3l

Thank you for your reply.

Discuss this with internal experts, The FXOSC is used as a source clock to a simple SoC counter with a configurable input clock division ratio in RTU.GPR.CFG_CNTDV and the counter output value is connected to Cortex-R52 CNTVALUEB. Typically FXOSC is 40Mhz and after reset CFG_CNTDV is 4. Hence: 40Mhz / 5 = 8 MHz inside Corter-R52 Generic Timer.

In addition, each RTU has its own counter and its divider and there is one Cortex-R52 Generic timer per RTU. 

Hope it can help you.

BR

Joey