Help with S32Z/E QSPI transmit buffer DMA operation

[AdamH_work]

After my last question on here, I've gotten the QSPI almost completely functional now.  I can read the SFDP parameters from the MT25QL256ABA8E12 on my S32E evaluation board and send IP commands to erase sectors.  I have AHB reads working and can view the contents of the flash at 0x10000000.  The final step is to get writes working.  I am adapting some older code originally written for the Kinetis K28F and it uses DMA to fill the transmit buffer in 16-byte/4-word chunks.

I have worked through getting my DMA driver set up, it's using DMA4 channel 0 with the DMA4_0_15_IRQ (114) interrupt and the QSPI1_TX mux source (28) for DMAMUX 4 channel 0.

I start by sending the write enable IP command, then I set the CLR_TXF bit in the MCR.  I then set up the DMA sequence to copy 4 words per block, bus width of 4 bytes (32-bit words), with the source address being the data in RAM and source address incrementing by 4 bytes each time, destination address being the QSPI1 TBDR register with destination address incrementing 0 to keep it at the same destination each time.  I enable the DMA, DMA interrupt, and mux channel.

Then, I send my IP command to perform a page program operation, which has already been configured in the LUT.  I wait for (FSMSTAT & 0x80000003) to equal 0x80000001 as described in the 65.14.3 TBDR register write lock section of the S32Z2 reference manual.  I then set the watermark value in TBCT (more on that later) and finally set the TBFDE bit in RSER which seems like it should trigger the DMA to start.

However, it does not appear that the DMA is triggered at all.  None of the DMA registers change, TBSR does not show any data filling the transmit buffer, and TBFDE does not automatically clear as it states it should in 65.14.3.

To verify my DMA configuration, I then tried manually starting the DMA by setting the START bit in the DMA channel's TCD CSR register.  If I have my total write size at only 16 bytes (one cycle of the DMA), it transfers all 16 bytes into TBDR and then triggers the DMA complete interrupt (114) as expected.  The QSPI executes the command and I can verify the first 16 bytes of the QSPI have changed.

However, if I increase my write beyond 16 bytes, it only writes the first 16 bytes and the DMA interrupt never triggers because the DMA only performs one cycle and stops.  I assume it is waiting on the hardware trigger from the QSPI to keep it going but this never happens.

I've studied the reference manual and the S32DS example code, but the example code does not appear to use DMA to fill the transmit buffer.  The reference manual section about the TX watermark is confusingly worded:

Watermark for TX buffer
Determines the watermark for the TX buffer
When the number of available space in the TX buffer is greater than or equal to the number provided by
WMRK (number of 4-byte entries). For example, a value of 0x1 sets the watermark to 4 bytes, 0x2 sets it
to 8 bytes, 0x3 sets it to 12 bytes, and so on. For details, see DMA usage.
WMRK = 0 is invalid.

As it is referring to "available space", I assume the value should be 256 - (number of words before triggering the DMA) which in this case should be 4 for 16 bytes?  Or should it be 255 - (number of words)?  I've tried a bunch of different values and none of them seem to make a difference.  I've tried 256-4, 255-4, 3, 4, 1, and 255.

What am I missing?

[AdamH_work]

Another thing to note, the Kinetis K28F datasheet's 35.8.6 DMA Usage section, DMA Usage in Normal Mode, describes both TX and RX configurations.  On the S32Z2 reference manual's equivalent section 65.7.4 DMA usage, it only describes RX configurations.  Does the S32Z2 QSPI even support filling the TX buffer using DMA?

[alejandro_e]

Hello again @AdamH_work,

Regarding the DMA support for writing, as long as you are using the memory mapped for the QSPI flash you should be able to use the DMA. About the watermark, it should be considered as 256 - WTMK. About the tests you did with more than 16 bytes, is the buffer aligned in memory to the size of the transfer? For your 16byte size, it should be aligned to 128 bit, for example all arrays are algined in the Mcl_DmaTransfer_AE_S32E2XX_R52 sample project.

When you are performing the transfers that fail (more than 16 bytes), are you getting any error flag in the registers?