Hello,
I am using the S32E288-975EVB and I am trying to use the R52_0 core as the boot core and run my application code from QSPI flash.
I could successfully boot my application code from flash with the M33 SMU core using the IVT tool. When I try to use the raw binary as my Application Bootloader in the R52_0 project IVT tool, I get the error "The size of the selected binary is greater than the maximum RAM size". The problem is most likely not the size, as I can successfully launch my code with the S32 Debug Probe and the code itself is a trivial LED blink.
I can also see that the binary is mostly empty in the beginning. There is some data at 0x0 - 0x20 and then it is just zeros until 0x0098_0000, which makes sense, because I can see from my linker file that DRAM starts at 0x3178_0000 and CRAM start at 0x3210_0000 (0x3210_0000 - 0x3178_0000 = 0x0098_0000):
/*
* Target device: This linker is demo and it is using for device S32Z2xx and S32E2xx only
* Target core: This linker target application which is running on RTU0 clusters for both split-lock and lockstep mode.
* Linker support for application running on single/multicore within RTU0 cluster by single image file. It need to align with MPU default setup in core.c as well.
* Memory setting: Local ram of RTU0 (CRAM and DRAM)
*/
/*
* GCC Linker Command File:
* 0x30000000 0x3000FFFF 65536 ; RTU0_R52_0_TCM_A
* 0x30100000 0x30103FFF 16384 ; RTU0_R52_0_TCM_B
* 0x30200000 0x30203FFF 16384 ; RTU0_R52_0_TCM_C
* 0x30400000 0x3040FFFF 65536 ; RTU0_R52_1_TCM_A
* 0x30500000 0x30503FFF 16384 ; RTU0_R52_1_TCM_B
* 0x30600000 0x30603FFF 16384 ; RTU0_R52_1_TCM_C
* 0x30800000 0x3080FFFF 65536 ; RTU0_R52_2_TCM_A
* 0x30900000 0x30903FFF 16384 ; RTU0_R52_2_TCM_B
* 0x30A00000 0x30A03FFF 16384 ; RTU0_R52_2_TCM_C
* 0x30C00000 0x30C0FFFF 65536 ; RTU0_R52_3_TCM_A
* 0x30D00000 0x30D03FFF 16384 ; RTU0_R52_3_TCM_B
* 0x30E00000 0x30E03FFF 16384 ; RTU0_R52_3_TCM_C
* 0x31780000 0x317C0000 262144 ; RTU0_DRAM_0 (Fast Data 0)
* 0x317C0000 0x31800000 262144 ; RTU0_DRAM_1 (Fast Data 1)
* 0x31800000 0x31880000 524288 ; RTU0_DRAM_2 (Fast Data 2)
* 0x32100000 0x321FFFFF 1048575 ; RTU0_CRAM_0 (Code ram 0)
* 0x32200000 0x322FFFFF 1048575 ; RTU0_CRAM_1 (Code ram 1)
* 0x32300000 0x323FFFFF 1048575 ; RTU0_CRAM_2 (Code ram 2)
* 0x32400000 0x324FFFFF 1048575 ; RTU0_CRAM_3 (Code ram 3)
* 0x32500000 0x325FFFFF 1048575 ; RTU0_CRAM_4 (Code ram 4)
* 0x32600000 0x326FFFFF 1048575 ; RTU0_CRAM_5 (Code ram 5)
* 0x32700000 0x327FFFFF 1048575 ; RTU0_CRAM_6 (Code ram 6)
* 0x79900000 0x799FFFFF 1048575 ; RTU0_CRAM_0_AXIF (Code ram 0 AXIF)
* 0x79A00000 0x79AFFFFF 1048575 ; RTU0_CRAM_1_AXIF (Code ram 1 AXIF)
* 0x79B00000 0x79BFFFFF 1048575 ; RTU0_CRAM_2_AXIF (Code ram 2 AXIF)
* 0x79C00000 0x79CFFFFF 1048575 ; RTU0_CRAM_3_AXIF (Code ram 3 AXIF)
* 0x79D00000 0x79DFFFFF 1048575 ; RTU0_CRAM_4_AXIF (Code ram 4 AXIF)
* 0x79E00000 0x79EFFFFF 1048575 ; RTU0_CRAM_5_AXIF (Code ram 5 AXIF)
* 0x79F00000 0x79FFFFFF 1048575 ; RTU0_CRAM_6_AXIF (Code ram 6 AXIF)
* 0x4E400000 0x4E400FFF 4096 ; AE_SRAM
*/
I have also tried to use the .elf format as the application bootloader in the IVT tool as I understand it basically helps reduce the unused space by defining RAM start sections with length and should reduce the amount of unused space in the binary, but I could not get it working as intended.
Now I have three main issues:
- Can I use the raw binary version for my application bootloader in the IVT TOOL or can the bootROM also interpret the .elf format correctly?
If I can not use the .elf format, then how can I make my raw binary usable? - When I am trying to boot from the R52_0 core, what should I set as RAM ENTRY pointer. The datasheet states "If Boot Target is 1, the allowed SRAM range for application download is in the RTU0 Code RAM region in the address range 3210_0000h to 327F_FFFFh.", so it has to be something in this range, but should it be set to Reset_Handler, ETABLE or VTABLE or something else entirely? For the M33 SMU core I had to set it as the start of VTABLE and then the VTABLE would point to Reset_Handler, but how does it work for the R cores?
- I feel like I have some mismatch of addresses. For example, I can see from the map file, that my exception vector table should be at 0x3210_0360:
*(.extable)
.extable 0x32100340 0x20 ./Project_Settings/Startup_Code/Vector_Table.o
0x32100340 ETABLE
0x32100360 . = ALIGN (0x4)
0x32100360 __exceptions_ram_end = .
0x32100360 __interrupts_ram_start = .
*(.intc_vector)
.intc_vector 0x32100360 0xf04 ./Project_Settings/Startup_Code/Vector_Table.o
0x32100360 DEFAULT_VECTOR
0x32101264 . = ALIGN (0x4)
0x32101264 __interrupts_ram_end = .
0x32101264 . = ALIGN (0x4)
*(.startup)
0x32101264 . = ALIGN (0x4)Since I don't have any interrupts defined it makes sense that every entry will point to undefined_handler, which I should be able to see from my raw_binary:
But undefined_handler address is set at 0x3210_14d0 in the map file:
0x321014ce HVC_Handler
0x321014d0 undefined_handler
*fill* 0x321014d2 0x2
.systeminit 0x321014d4 0x124 ./Project_Settings/Startup_Code/system.o
Will it be a problem or is that off by one error somehow accounted for somewhere else?
