Hello @Rudved_3366,
Regarding your initial request involving an error injection into SRAM0, please refer to the EMI_2_CH_0 definition in the Reference Manual.

EMCEM_EIM_2_CH_0 targets SRAM0 and provides access to 64 data bits and 8 check bits.
You configured:
eMcem_SetupInjectionChannel(EMCEM_EIM_2_CH_0, 55U, 66U);
According to the Error Injection Channel Descriptor n, Word0 (EICHD0_WORD0 – EICHD4_WORD0) description in the Reference Manual:
Data bit index 55 corresponds to WORD[1], bit 23.
Check bit index 66 corresponds to WORD[0], bit 26.
As a result, the injection setup inverts one data bit and one check bit in SRAM0. In this configuration, the generated fault pattern is interpreted as an uncorrectable ECC error, which is reported by ERM0_CH0.
Regarding DTCM_1.
It seems to be all correct.
The ERM channel identifies the error source, in this case CH12 corresponds to DTCM1.
The ERM address is the latched address associated with that channel, not a complete global address.
Regards,
Daniel