Hi @piyush1
I have reviewed your code and configuration and would like to share a few observations.
The I2C clock source has been set to CORE_CLK, but the actual source is AIPS_SLOW_CLK. You can confirm this in the Clock Tree within the Clock Tool of ConfigTools or refer to Figure 75 in the S32K3xx Reference Manual, Rev. 11.
Also, when working in polling mode, I recommend separate devices for master and slave, as in this mode, the master continuously checks for the end of transmission or incoming data without interrupts, which can affect.
While there is not a dedicated example for your specific setup, there are two example codes available for S32K1 devices using the S32SDK for S32K1xx. These examples implement similar functionality and can serve as a helpful reference, as the I2C module is similar across these families.
BR, VaneB