s32k146 RCM-SSRS SWDOG Abnormal Set

[luhaiou]

Dear NXP,

My target chip is S32K146.

When I am debugging online, the program hasn't run yet and stops at the beginning of the main function.

I found that the RCM-SSRS SWDOG was set.

RCM-SSRS SWDOG is only set after the first click on the debug button. It is normally cleared after clicking the restart button.

Looking forward to NXP's explanation, thank you very much.

[Julián_AragónM]

Hi @luhaiou,

The SSRS bits include status flags to indicate all reset sources since the last POR or LVD
that have not been cleared by software. 

Also, the SWDOG bit reads: Indicates a reset has been caused by the watchdog timer timing out. This reset source can be blocked by disabling the watchdog.

This means that the WDOG runs and expires before connecting the debugger. If you are using S32K1 SDK, you can use the DISABLE_WDOG symbol to disable the WDOG: S32K118 Watchdog Issue.

Best regards,
Julián

[luhaiou]

I have already used the DISABLE_WDOG symbol to disable the WDOG.

But When I am debugging online, the program hasn't run yet and stops at the beginning of the main function.

I found that the RCM-SSRS SWDOG was set.

RCM-SSRS SWDOG is only set after the first click on the debug button. It is normally cleared after clicking the restart button.

Looking forward to NXP's explanation, thank you very much.

[Julián_AragónM]

Hi @luhaiou,

What is inside your routine? Does this also happen with an example code? After starting debug session, debugger should assert reset by external pin:

Do you clear the RCM-SSRS register by code anywhere? Also, please share which SDK or RTD version you are using so I can test it on my side.

Best regards,
Julián