question about external oscillator stops

[ivyxx]

I use System PLL as external oscillator as my system clock in S32K146, and I open the clock monitor of SPLL. If I set SCG_SOSCCSR_SPLLCMRE as 0, which means an interrupt is generated when error detected.

What will happen after interrupt? Can S32K146 switch to internal oscillator when the interrupt is generated? 

[Senlent]

Hi@ivyxx

I know what you mean, but I think the MCU needs to enter the software reset to switch other clocks when the clock fails.

BR!

       Jim.

[Senlent]

Hi@ivyxx

     In S32K14x, there are two clock monitors, 1) SOSC Loss-of-Clock monitor and 2) SPLL Loss-of-Lock monitor. 
     Those monitors can be enabled with SCG_SOSCCSR[SOSCCM]=1 and SCG_SPLLCSR[SPLLCM]=1 respectively. 
     Once those monitors detected abnormal behaviors in SOSC/SPLL, the flags SCG_SOSCCSR[SOSCERR] and/or SCG_SPLLCSR[SPLLERR] are asserted, and generate interrupt or reset as summarized below.

Please note interrupt should not be selected if SOSC/SPLL clocks are used as system clock.

refer to 'Clock monitoring for functional safety' and this answer posted by r11172

Best regards,

         Jim,

[ivyxx]

Hi  jim,

Thanks for your reply.

When SPLL is chosen as system clock, the system can only generate reset when clock loss happens. So that if clock loss always happens, the system will reset continuously, right? Is there any chance to avoid it?

[Senlent]

Hi@ivyxx

         Please refer to this answer.

https://community.nxp.com/t5/S32K1-KEA-Internal-Community/Clock-monitoring-for-functional-safety/m-p... 

BR！

 Jim.

[ivyxx]

Hi jim:

 I do not have access to this page.