power mode switch failed

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power mode switch failed

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maojun
Contributor II

MCU:S32k144

SDK :0.8.6

I want to know that what is the effection when power mode switch failed .For example, I changed power mode from HSRUN  to RUN ,if it fails.what will happened? whether system can not wakeup if system go to VLPS mode failed?

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dianabatrlova
NXP TechSupport
NXP TechSupport

Hello,

At first, please use the newest SDK:

https://community.nxp.com/docs/DOC-343020 

If the change of power modes failed the system stay in RUN mode.

There is a PMSTAT register which indicates the current power mode of the system, see section "39.3.6 Power Mode Status register (SMC_PMSTAT)" in the RM rev. 9.

Regarding VLPS there is VLPSA field :

"This field is cleared by reset or by hardware at the beginning of any stop mode entry sequence and is set if the sequence was aborted. "

Note: stop mode is not supported by HSRUN.

I hope it helps,

Best Regards,

Diana

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maojun
Contributor II

Our project has been mass produced,so it is unlikely to replace the newest sdk.

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dianabatrlova
NXP TechSupport
NXP TechSupport

Hello,

I understand, but in the older versions, some issues can exist which are fixed in the new versions.

The system clock before the transition to VLPS is not correctly reconfigured in this SDK v0.8.6.

When the transition to VLPS it is recommended to disable the PLL, FIRC, and SOSC.

I hope it helps.

Best Regards,

Diana

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maojun
Contributor II

Hello,

Condition Description: 

I set power mode from HSRUN to RUN mode,then I set external pin interrupt of PTE.4,PTE.0,PTE.8. After all this complete,I set power mode from RUN to VLPS mode.

Question:

Is it possible to have an interruption of PTE.0/PTE.4/PTE.8, but not wake up from vlps mode?

If you have been received my message ,please answer this question. It is very important to us.Thanks a lot.

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dianabatrlova
NXP TechSupport
NXP TechSupport

Hello,

At first, please, make sure that the FIRC, SOSC, and SPLL clocks are disabled in VLPS mode. If not it may lead to the mode transition to fail.

Please refer to the section "27.4.4 VLPR/VLPS mode entry"

"When entering VLPR/VLPS mode, the system clock should be SIRC. The FIRC, SOSC,
and SPLL must be disabled by software in RUN mode before making any mode
transition."

The FIRCREGOFF bit is not being correctly configured in the SDK v0.8.6. 

Thank you.

Best Regards,

Diana

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maojun
Contributor II

I see ,thanks

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maojun
Contributor II

Hi  Diana,

Thank you for your information.

Could you please give me more information about  "The system clock before the transition to VLPS is not correctly reconfigured in this SDK v0.8.6." And do you mean we need to disable the PLL,PIRC and SOSC when we switch power mode to VLPS  to avoid  self problems of  sdk 0.8.6.  If the switch to VLPS fails, will it fail to wake up by external interrupt?and MCU  can not wake up again except  reset?

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