pcssck

[hajianik]

Target is S32K148.

I'm trying to do an SPI transfer consisting of 5 bytes(40 bits) where the CS is asserted for the duration of transfer. The baud rate is  4mhz, peripheral Clock is PLL and Divider is 1 and peripheral Clock frequency is 40mhz , using SPI0 for this I have the following in LPSPI0_CCR:

SCKDIV 0X08

DBT 0X04

PCSSCK 0X03

SCKPCS 0X03

Using these values results in an uneven clock and longer CS assertion period. when I twig these parameters the clock changes but I am not able to achieve the desired symmetrical with desired CS AASERTION DURATION OF 10 US. please look at attachment for the Screenshot

[danielmartynek]

Hi,

I understand the asymmetricity is in the SCK-to-PCS Delay / PCS-to-SCK Delay.

But this can't be seen in the screenshot.

Can you measure it with an oscilloscope and an active probe?

Do you use the High-Drive pins? PCR[DSE] = 1.

S32K148 IO_Signal_Description_Input_Multiplexing.xlsx

Thanks,

BR, Daniel

[hajianik]

Hi Daniel,

Thanks for your quick response,

In the screen shot the clock(red color) is not a%50 duty signal, Can't you see that?

when you say:

"I understand the asymmetricity is in the SCK-to-PCS Delay / PCS-to-SCK Delay"

You mean there are not the same?

Yes they are not the same.

I will measure it and I use hi drive pins for the clock signal and let you know.

Thanks,

Koorosh

[danielmartynek]

Hi Koorosh,

If you mean the 74.63% duty, it is not given by the SCK-to-PCS, PCS-to-SCK delays.

For example, PCS-to-SCK is just the delay from the PCS assertion to the first SCK edge.

The 35.6us delay is most likely caused by the CPU overhead.

The SW must prepare another 40b transfer and it takes some time.

Regards,

Daniel