Hi, I am using the MK10DX256VLQ10 processor. I have configured my FlexRam the following way:
int partition_flash(void)
{
/* Test to make sure the device is not already partitioned. If it
* is already partitioned, then return with no action performed.
*/
if ((SIM->FCFG1 & SIM_FCFG1_DEPART(0xF)) != 0x00000F00)
{
return 0;
}
//PARITITION NOTE SETTING MUST ALSO BE MADE IN DEBUG CONFIG FOR THIS TO WORK
// Wait for the command to complete
while(!(FTFL->FSTAT & FTFL_FSTAT_CCIF_MASK));
// Write the FCCOB registers
FTFL->FCCOB0 = FTFL_FCCOB0_CCOBn(PROG_PARITION_CMD); // Selects the PGMPART command
FTFL->FCCOB1 = 0x00; //not used for this command
FTFL->FCCOB2 = 0x00; //not used for this command
FTFL->FCCOB3 = 0x00; //not used for this command
// FCCOB4 is written with the code for the subsystem sizes (eeprom_size define)
FTFL->FCCOB4 = EE_SIZE_4K | EE_SPLIT;
// FFCOB5 is written with the code for the Dflash size (dflash_size define)
FTFL->FCCOB5 = EE_FLASH_32K;
// All required FCCOBx registers are written, so launch the command
FTFL->FSTAT = FTFL_FSTAT_CCIF_MASK;
// Wait for the command to complete
while(!(FTFL->FSTAT & FTFL_FSTAT_CCIF_MASK));
// Protection error clear it
if ((FTFL->FSTAT & FTFL_FSTAT_FPVIOL_MASK) == FTFL_FSTAT_FPVIOL_MASK)
{
FTFL->FSTAT |= FTFL_FSTAT_FPVIOL_MASK;
}
// if there is an access error clear it
if ((FTFL->FSTAT & FTFL_FSTAT_ACCERR_MASK) == FTFL_FSTAT_ACCERR_MASK)
{
FTFL->FSTAT |= FTFL_FSTAT_ACCERR_MASK;
}
// if there is a read/write collision error
if ((FTFL->FSTAT & FTFL_FSTAT_RDCOLERR_MASK) == FTFL_FSTAT_RDCOLERR_MASK)
{
FTFL->FSTAT |= FTFL_FSTAT_RDCOLERR_MASK;
}
return 1;
}
This code appears to work fine. However, during power up I check to see if my EEPROM are all empty. If they are I attempt to write default values.
My eeprom write function looks like:
void EEE_Write_uint32(uint32_t data, uint32_t *target)
{
// Protection error clear it
if ((FTFL->FSTAT & FTFL_FSTAT_FPVIOL_MASK) == FTFL_FSTAT_FPVIOL_MASK)
{
FTFL->FSTAT |= FTFL_FSTAT_FPVIOL_MASK;
}
// if there is an access error clear it
if ((FTFL->FSTAT & FTFL_FSTAT_ACCERR_MASK) == FTFL_FSTAT_ACCERR_MASK)
{
FTFL->FSTAT |= FTFL_FSTAT_ACCERR_MASK;
}
// if there is a read/write collision error
if ((FTFL->FSTAT & FTFL_FSTAT_RDCOLERR_MASK) == FTFL_FSTAT_RDCOLERR_MASK)
{
FTFL->FSTAT |= FTFL_FSTAT_RDCOLERR_MASK;
}
while ((FTFL->FSTAT & FTFL_FSTAT_CCIF_MASK) == 0){}
*target=data;
FTFL->FSTAT |= FTFL_FSTAT_CCIF(1);
}
This code also works fine as long as I insert delays in between write attempts. Based on reading the documentation I should see the CCIF bit is 1 when the function is entered and at the end since I wrote a 1 to the CCIF it should be busy blocking the next call until it finishes. However, CCIF is never changing state so concurrent write trigger the fault error handler in the processor.
Am I don't something wrong in checking if the system is ready for another EEPROM write?
Hi @pbaierlac
Thank you so much for using our community. We are overloaded on the number of request these days, so I really really appreciate your patience.
Regarding your issue, it comes to my mind that you are setting that 1 to CCIF wrongly, because based on the documentation you should see the CCIF bit is 1 when the function is entered and at the end, and it is unclear to me why you are writting a 1 to that register? Probably, that's why it is throwing you to a fault error handler.
Please let me know your comments and if it is possible may you tell me what are you trying to do? Because it is still unclear to me. Also, if you have more questions, I would be more than happy to assist you.
Thanks in advance.
Sincerely,
Pablo Avalos.