WDOG cannot use 8-bit sequence refresh

[GXY]

I am unable to use 4 8-bit writes to refresh the watchdog of S32K144. Both 16 bit and 32-bit are acceptable, but 8-bit is not. I tried the 8-bit writing method in the picture, but it all failedThe original manual is as follows:

The refresh write sequence can be
• either two 16-bit writes ( 0xA602, 0xB480) or four 8-bit writes (0xA6, 0x02, 0xB4,
0x80) if WDOG_CS[CMD32EN] is 0;
• one 32-bit write (0xB480_A602) if WDOG_CS[CMD32EN] is 1.
to the CNT register. Both methods must occur before the WDG timeout; otherwise, the
watchdog resets the MCU.

[danielmartynek]

Hi @GXY,

The WDOG supports an 8-bit refresh sequence, but it is highly timing-sensitive. Even if standard C code generates STRB instructions, the sequence can fail due to additional stack accesses or address reloads inserted between the byte writes. Using a compact GCC inline assembly block helps ensure the 8-bit refresh executes reliably.

static inline void WDOG_Refresh8_AsmInline(void)
{
 __asm volatile(
 // "mrs r2, PRIMASK \n"
 // "cpsid i \n"
 // "dsb \n"

 "ldr r0, =0x40052004 \n"

 "movs r1, #0xA6 \n"
 "strb r1, [r0, #1] \n"

 "movs r1, #0x02 \n"
 "strb r1, [r0, #0] \n"

 "movs r1, #0xB4 \n"
 "strb r1, [r0, #1] \n"

 "movs r1, #0x80 \n"
 "strb r1, [r0, #0] \n"

 // "dsb \n"
 // "isb \n"
 // "msr PRIMASK, r2 \n"
 );
}

Regards,

Daniel

[db16122 · Accepted solution]

Before starting the refresh sequence, disable the global
interrupts. Otherwise, an interrupt could effectively invalidate
the refresh sequence, if the interrupt occurs before the refresh
writes finish. After the sequence finishes, restore the global
interrupt control state.  FYI for interrupt checking

[GXY]

I confirm that the switch was interrupted before and after feeding the dog. In the same scenario, only changing the feeding sequence and using the 16 bit feeding method succeeded, but the 8-bit feeding method failed, and adjusting the order of the 8-bit feeding sequence did not work.