Hi @HectorNadal
On WDOG timeout, the WDOG module immediately requests a reset in the Reset Control Module (RCM). So, if the WDOG counter is not refreshed, its interrupt triggers a reset.
VaneB_0-1693511761807.png
The reset request to RCM can be delayed by 128 bus clock cycles if the WDOG interrupt is enabled (WDOG_CS[INT] = 1). If enabled, the WDOG interrupt vector is fetched or becomes pending in NVIC. After the delay, the reset is requested in RCM.
If you want to force a reset, set the Wdg Trigger Condition (Wdg_43_Instance0_SetTriggerCondition) just once to generate a timeout.
B.R.
VaneB