Tresos computes the wrong QSPI_SFCK_CLK clock frequency

[maria_beatrice_balaceanu]

Hi,

I am trying to replicate an S32 Design Studio Mcu configuration into a Tresos project for S32K396. The clock configuration is Option A+ - High Performance mode from the RM, I need it in order to use the QSPI module. I am using Tresos 29.0.0, with RTD SW32K3_RTD_4.4_R21-11_3.0.0.

The problem I have encountered with Tresos is that, in Mcu/McuSettingConfig/McuClockSettingConfig_0/McuCgm0ClockMux10, the value of the clock frequency is not computed correctly (figure 1_DesignStudio_vs_Tresos_config.png).

PLL_PHI1_CLK has the same frequency for both the Design Studio and the Tresos configurations (480 MHz - it has also been checked via debugging). For the QSPI_SFCK_CLK, when I set the CGM0 Clock Mux10 Divisor0 to 0, Tresos computes a frequency of 240 MHz instead of 120 MHz and throws an error stating that it "must be >= 0 and <= 120000000 (calculated by ecu:get('MCU.AuxClock.Limits.QuadSPI_SFCK'))" (figure 2_Tresos_value_out_of_range). If I try setting the 120 MHz value of the frequency manually, I get an error stating that the "McuClockMux10Divider0_Frequency is out of range" (figure 3_Tresos_value_out_of_range.png).

I tried leaving the CGM0 Clock Mux10 Divisor0 to 1, Tresos displayed a frequency of 1.2E8, but, upon debugging, I have noticed that the QSPI_SFCK_CLK frequency is half of the value computed in Tresos (figure 4_wrong_frequency_value). Additionally, because of this divisor difference, the Tresos generated code (generate/src/Clock_Ip_*_cfg.c) differs from the one of Design Studio (figure 5_QSPI_divider_Tresos_vs_S32DS.png).
This wrong Tresos frequency leads to a hardfault when trying to initialize the Mem_43_ExFls module.

I have the same frequency computation issues with McuCgm0ClockMux15 and McuCgm0ClockMux16.

Could you kindly help me with this?

Thank you!

[cuongnguyenphu]

I  recommend to to use the Im-and Exporter in EB Tresos to import config from S32DS.
Please follow these step:

Step 1: 
1. In S32DS, select Peripherals tool, then select Global settings
2. Under SystemModel, select EcvdGenerationMethod as INDIVIDUAL
3. Select directory to store your ECVD output file (ecvd is the file contains configurations of each module in your S32DS's project)
4. Click on Generate Configuration button

cuongnguyenphu_0-1699873683447.png

-> ECVD files will be generated 

STEP 2. Import Ecvd files to EB Tresos:
1. In Project Explorer window of EB Tresos, Right-click on project you're working on, then select Im-and Exporter:

cuongnguyenphu_1-1699873904622.png
2. Click  Create new Im/ Exporter > Next > :

cuongnguyenphu_2-1699874021387.png

3. Browse to the ecvd file which is generated from previous Step > Next:

cuongnguyenphu_3-1699874110451.png

4. Enable path mapping + Use automatically... > Finish

cuongnguyenphu_4-1699874180912.png

5. Select the Importer which just created and click on Run Importer:

cuongnguyenphu_5-1699874251371.png

After this step, all configuration in ECVD file would be import into the module you're working on. 

[maria_beatrice_balaceanu]

Hi, @cuongnguyenphu ,

Thank you! I have followed your instructions and imported the Design Studio Mcu module into Tresos successfully. However, even with the imported configuration, Tresos still throws me the same "out of range" error for McuCgm0ClockMux10 (which is related to QSPI_SFCK_CLK), McuCgm0ClockMux15 and McuCgm0ClockMux16. I have attached a screenshot of the issue in 1_Mcu_CGM_Clk_out_of_range.png.

Could you kindly help me with this?

Thank you,

Beatrice

[cuongnguyenphu]

Can you share me the configuration file of Mcu? I would like to check from my side

[maria_beatrice_balaceanu]

Hi, @cuongnguyenphu ,

Sure, I have attached it here. Thank you!

[cuongnguyenphu]

The value describes in EB Tresos is differ than S32DS:
- In EB Tresos:
This value presents value of QSPI_2XSFIF:

cuongnguyenphu_0-1700125217985.png

In S32DS:
This value presents for QuadSPI_SFCK:

cuongnguyenphu_1-1700125324522.png

As RM of S32K396,  QSPI_SFCK equals of 1/2 value of  QSPI_2XSFIF :

cuongnguyenphu_2-1700125409787.png

That's why you see the difference between EB Tresos and S32DS.
It also explains why you see the value in EB Tresos is differ than when you use Mcu_GetClockFrequency(QSPI_SFCK_CLK):

cuongnguyenphu_3-1700125526765.png

I will raise an internal ticket for our team to describe more clearly this note in EB Tresos and S32DS to avoid the confuse of user on this.
Another issue regarding to the Out of range value when import ECVD file into EB Tresos will be reported to our team also. The reason is that in S32DS, we don't check range for these value, but it does in EB Tresos. So with the same Out of range value, only error in EB Tresos raised. The workaround for this is you can select another Divider value and Re-calculate the these errors again to make it works in EB Tresos:

cuongnguyenphu_4-1700125822300.png

[maria_beatrice_balaceanu]

Hi, @cuongnguyenphu ,

Thank you for your clarification! I have tried this workaround, but, unfortunately, the "Value out of range" error persists. In our case, if QSPI_SFCK_CLK=1.2e8, we need QSPI_2XSFIF to be 2.4e8. When we set the divider to 0, Tresos computes the correct value for QSPI_2XSFIF (2.4e8), but the error still appears and we cannot generate the code we need (1_workaround_attempt.png). 

Could you kindly offer us an estimation of when these Tresos fixes will be available?

Thank you!

[cuongnguyenphu]

The internal team has noticed this issue about the range of QSPI_2XSFIF limit to 120Mhz
They planned to fix it in next release by the end of this month. The version should be RTD S32K3_S32M27x 4.7 4.0.0 which support for S32K396 also
If you need the workaround, I think you can set the QSPI_2XSFIF to 120Mhz then generate code for this first,
Then you can change the divider value in generated file to make it becomes 240Mhz

cuongnguyenphu_0-1700213361206.png