Hi,
I am trying to replicate an S32 Design Studio Mcu configuration into a Tresos project for S32K396. The clock configuration is Option A+ - High Performance mode from the RM, I need it in order to use the QSPI module. I am using Tresos 29.0.0, with RTD SW32K3_RTD_4.4_R21-11_3.0.0.
The problem I have encountered with Tresos is that, in Mcu/McuSettingConfig/McuClockSettingConfig_0/McuCgm0ClockMux10, the value of the clock frequency is not computed correctly (figure 1_DesignStudio_vs_Tresos_config.png).
PLL_PHI1_CLK has the same frequency for both the Design Studio and the Tresos configurations (480 MHz - it has also been checked via debugging). For the QSPI_SFCK_CLK, when I set the CGM0 Clock Mux10 Divisor0 to 0, Tresos computes a frequency of 240 MHz instead of 120 MHz and throws an error stating that it "must be >= 0 and <= 120000000 (calculated by ecu:get('MCU.AuxClock.Limits.QuadSPI_SFCK'))" (figure 2_Tresos_value_out_of_range). If I try setting the 120 MHz value of the frequency manually, I get an error stating that the "McuClockMux10Divider0_Frequency is out of range" (figure 3_Tresos_value_out_of_range.png).
I tried leaving the CGM0 Clock Mux10 Divisor0 to 1, Tresos displayed a frequency of 1.2E8, but, upon debugging, I have noticed that the QSPI_SFCK_CLK frequency is half of the value computed in Tresos (figure 4_wrong_frequency_value). Additionally, because of this divisor difference, the Tresos generated code (generate/src/Clock_Ip_*_cfg.c) differs from the one of Design Studio (figure 5_QSPI_divider_Tresos_vs_S32DS.png).
This wrong Tresos frequency leads to a hardfault when trying to initialize the Mem_43_ExFls module.
I have the same frequency computation issues with McuCgm0ClockMux15 and McuCgm0ClockMux16.
Could you kindly help me with this?
Thank you!